A Highly Integrated 60GHz CMOS Front-End Receiver

Emami, S.; Doan, C.H.; Niknejad, Ali M.; Brodersen, R.W.

doi:10.1109/isscc.2007.373358

Cited by 113 publications

(31 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A prior study showed that the three-cascaded LNA designed in the 60 GHz front-end receiver consumed 43.2 mW with minimum noise figure of 8.8 dB providing 12 dB peak power gain [1]; however, the high power dissipation and high noise figure were the two major issues for V-band receivers. In another study, the single stage V-band LNA exhibited 9.6 mW power dissipation and 5 dB gain [2].…”

Section: Introductionmentioning

confidence: 99%

Ultra low power and highly linearized LNA for V-band RF applications in 180 nm CMOS technology

Khaleel

Abbas

2017

IEICE Electron. Express

View full text Add to dashboard Cite

In this study, the common gate stage of the conventional inductive degeneration cascode LNA operating in 60 GHz V-band for the upcoming Wi-Fi standard, and 802.11ad standard with data rates up to 7 Gbit/sec was linearized by bilateral CMOS resistor. The proposed method linearizes the LNA by 6 dBm with minimum power consumption. The proposed LNA dissipates only 2.05 mW supplied from 1.8 V voltage source and exhibits a minimum noise figure of 6.8 dB in the operating frequency. The LNA, without the proposed linearization technique, exhibited 7 dB gain. The linearized LNA exhibited 3.5 dB gain. The ADS2016.01 with TSMC 180 nm CMOS model files were used to perform the simulation.

show abstract

Section: Introductionmentioning

confidence: 99%

Ultra low power and highly linearized LNA for V-band RF applications in 180 nm CMOS technology

Khaleel

Abbas

2017

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Since it has become feasible to design integrated circuits operating at 60 GHz using CMOS processes at the 0.13 m node and beyond [1], many applications for the consumer market have been conceived to make use of the large available bandwidth. The new field of millimeter-wave (mmWave) radio design in CMOS has required innovations at all levels of RF design, from device modeling, to circuit design, to system architecture.…”

Section: Introductionmentioning

confidence: 99%

A low power 60GHz OOK transceiver system in 90nm CMOS with innovative on-chip AMC antenna

Lin

Brinkhoff

Kang

et al. 2009

2009 IEEE Asian Solid-State Circuits Conference

View full text Add to dashboard Cite

Building on an efficient active and passive device modeling strategy, a 60 GHz OOK transceiver system including on-chip antenna in 90nm CMOS is designed. The key features of the circuits are small power consumption and size. With the modulator connected to an innovative artificial magnetic conductor (AMC) on-chip antenna, free space transmission at 2Gb/s is demonstrated. Also, an on-chip psuedo-link demonstrates 1Gb/s transmission, using only 26 pJ/bit for the modulator and 6 pJ/bit for the demodulator. The receiver consists of on-chip antenna, LNA with 20dB gain & 5.7dB noise figure, detector and limiting amplifier. Recovery of a 1.5Gb/s NRZ signal is demonstrated.Index Terms -Millimeter-wave CMOS, RF modeling, modems, transceiver, amplitude-shift keying, scalable models, artificial magnetic conductor, on-chip antenna and system on chip

show abstract

“…Active and passive components, building blocks, and transceiver front-ends are being intensively investigated [3]- [10]. The choice of the best suited transceiver architectures still entails several considerations.…”

Section: Introductionmentioning

confidence: 99%

Analysis and Design of a Double-Quadrature CMOS VCO for Subharmonic Mixing at $Ka$-Band

Mazzanti

Sacchi

Andreani

et al. 2008

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

Abstract-In this paper, we analyze the potentials of a four-phase 14-GHz CMOS voltage-controlled oscillator, tailored to a subharmonic receiver, for signal processing at -band. When mild phase accuracies between in-phase and quadrature down-converted signals are required, the four-phase oscillator displays roughly the same phase noise figure-of-merit as quadrature oscillator counterparts. However, the operation at half-frequency leads to an improved performance due to a higher quality factor of the tuning varactors, and because the local oscillator circuitry and signal path run at different frequencies, relaxing coupling issues. A detailed time-variant analysis of phase noise in multiphase oscillators is introduced and validated by both simulations and experiments.Prototypes realized in a 65-nm technology occupy an active area of 0.5 mm 2 and show the following performances: a 26% frequency tuning range (from 12.2 to 15.9 GHz), maximum phase error from 4 of 2 , and a phase noise of 110 dBc/Hz at 1 MHz from 14 GHz, while consuming 18 mA from 0.8-V supply.

show abstract

A Highly Integrated 60GHz CMOS Front-End Receiver

Cited by 113 publications

References 4 publications

Ultra low power and highly linearized LNA for V-band RF applications in 180 nm CMOS technology

Ultra low power and highly linearized LNA for V-band RF applications in 180 nm CMOS technology

A low power 60GHz OOK transceiver system in 90nm CMOS with innovative on-chip AMC antenna

Analysis and Design of a Double-Quadrature CMOS VCO for Subharmonic Mixing at $Ka$-Band

Contact Info

Product

Resources

About