A Highly-Efficient Error Detection Technique for General Matrix Multiplication using Tiled Processing on SIMD Architecture

Mummidi, Chandra Sekhar; Bal, Sandeep; Goldstein, Brunno F.; Srinivasan, Sudarshan; Kundu, Sandip

doi:10.1109/iccd56317.2022.00084

Cited by 1 publication

(2 citation statements)

References 31 publications

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“…Proactive hardware-based Reactive hardware-based Cross-layer Model training modification [61], [90], [91], [202]- [223] Memory cell re-design [224], [225] Weight-shifting [226] Model/hardware co-design [227], [228] Model modification [229]- [231] Memory aging mitigation [232] Re-learning [233] Fault-aware pruning with retraining [95] Fault-tolerant model search [234] Activation clipping [57], [81], [235]- [238] Algorithmic-based fault-tolerance [81], [239]- [244] Fault-aware mapping [101],…”

Section: Model-basedmentioning

confidence: 99%

“…3) Algorithmic-based fault tolerance: Algorithmic-Based Fault Tolerance (ABFT), originally proposed in [279], is a low-cost solution for detecting and correcting abnormal behavior in matrix-matrix multiplications based on checksums. As neural network operation heavily relies on matrix-matrix multiplications, ABFT finds a natural application for enabling fault-tolerance in AI hardware accelerators with several ABFT schemes being proposed to date in the literature [81], [239]- [244].…”

Section: Reactive Hardware-based Approachesmentioning

confidence: 99%

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Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives

Liu

Stratigopoulos³

2023

IEEE Des. Test

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In recent years, there has been an expedited trend in embracing bold and radical innovation of computer architectures, aiming at the continuation of computing performance improvement despite the slowed-down physical device scaling. One new frontier in this field focuses on Artificial Intelligence (AI) hardware. While functionality of AI hardware still remains the main focus, testability and dependability of these new architectures need to be addressed before the mainstream adoption. This survey paper covers the state-of-the-art in research and development of dependability and testability solutions for AI hardware including digital or analog implementations of Artificial Neural Networks (ANNs) and Spiking Neural Networks (SNNs), used in accelerators and neuromorphic designs. Trends, challenges and perspectives are also discussed in this paper.

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