A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter

Chao, Yei Chin; Lin, Ji-Kun; Yang, Jar‐Ferr; Liu, Bin-Da

doi:10.1109/apccas.2006.342392

Cited by 7 publications

(3 citation statements)

References 8 publications

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“…The architectures developed by Chao [10] and Khurana [5] benefit from a novel filtering order, and, hence, the local memory required is reduced. Li [9], Lin [7], and Bojnordi [11] proposed special multi-bank memory organizations to save the use of transpose registers.…”

Section: Hardware Costmentioning

confidence: 99%

“…Li [9] proposed a four-stage pipelined data path that is 47% faster than a nonpipelined data path. Chao [10], Bojnordi [11] and Khurana [5] proposed pipelined edge filters with a hazard-free filtering order. Our previous design [6] utilizes a forwarding scheme that prevents pipeline hazards.…”

Section: Working Frequencymentioning

confidence: 99%

“…Probabilistic approach to estimate power was proposed in [9] to overcome input pattern dependence and used a zero-delay model. Probabilistic approaches [10]- [14] that did not assume zero-delay were proposed to handle glitches. To consider temporal correlations, such approaches specify the probability of switching at specific time points at circuit inputs [15].…”

Section: Introductionmentioning

confidence: 99%

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A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder

Lin

2009

IEEE Trans. VLSI Syst.

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We propose a high-performance hardwired deblocking filter for H.264/AVC decoding. To decode QFHD (3840 2160, i.e., four times full HD) ultra high definition video, we minimize number of processing cycles, working frequency and amount of external memory traffic. We propose a novel filtering order and employ a 5-stage pipelined and resource-shared dual-edge filter to generate two filtering results every cycle. Taking advantage of skip modes, our filter takes only 48 cycles to filter a macroblock in the best case and 100 in the worst case. Furthermore, it eliminates most unnecessary off-chip memory traffic with a novel on-chip memory scheme. Our design can support QFHD at 30 fps application by running only at 98 MHz.

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