A high-speed real-time binary BCH decoder

Wei, Shyue‐Win; Wei, Che‐Ho

doi:10.1109/76.212719

Cited by 17 publications

(21 citation statements)

References 6 publications

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“…Cyclic Redundancy Check (CRC) Cyclic Redundancy Check [8] is a hash function to generate a fixed length of verification code. It bases on calculating network packets or digital files to verify those data whether errors occur or not.…”

Section: Amentioning

confidence: 99%

Power line communication chip design with data error detecting/correcting and data encrypting/decrypting ability

Kuo

Hsu

2012

2012 International Symposium on Intelligent Signal Processing and Communications Systems

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This paper presents a low cost chip design of Power Line Communication for the applications in the home networks. The data transmission occur burst errors easily by the noise interference from the environment. In order to reduce the error rate, an all-digital modulation/demodulation chip with error correctable and high error detected ability for power line communication is designed. The proposed design consists of Cyclic Redundancy Check, Digital Pulse Width Modulation, Digital Frequency Shift Keying, Forward Error Correction, interleaving techniques, and Tiny Encryption Algorithm. The fabricated chip area is 1.352 mm 2 with 3.3/1.8 supply voltages. The measured data shows that the proposed design is fully functional and consumes 70 μW.

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Section: Amentioning

confidence: 99%

Power line communication chip design with data error detecting/correcting and data encrypting/decrypting ability

Kuo

Hsu

2012

2012 International Symposium on Intelligent Signal Processing and Communications Systems

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“…r and 0 r , corresponds to S2 = "1000"; CG1, consisting of û 3 , 6 r and 1 r , corresponds to S2 = "0100"; CG2, consisting of û 4 , 7 r and 2 r , corresponds to S2 = "0010"; CG3, consisting of û 5 ,û 0 and 3 r , corresponds to S2 = "0001"; CG4, consisting of û 6 ,û 1 and 4 r , corresponds to S2 = "1111"; Therefore, the recognition of a CG can be based on the position of bit "1" in S2.…”

Section: Cg0 Consisting Ofû 2 mentioning

confidence: 99%

“…Hence, this is called an iterative method of decoding. Even though the hardware implementation [7] is less complex than that of the first decoding algorithm, the throughput may not be higher due to the iterative procedures.…”

Section: Introductionmentioning

confidence: 99%

A Low-Complexity and High-Throughput RTL Design of a BCH (15,7) Decoder

Setiawan

2012

itbj.ict.

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Abstract. The Bose, Chaudhuri and Hocquenghem (BCH) codes form a large class of powerful random-error correcting cyclic codes. However, the implementation of its decoder requires high-complexity computation resources with a huge number of sequential circuits. This paper presents a low-complexity register transfer level (RTL) circuit design of a BCH decoder. In accordance with the table relationship between the syndrome and the error bit position, we propose a circuit that is mostly occupied by combinational elements without any sequential evolvement. Therefore the designed system has a low complexity and high throughput properties. The implementation of the BCH (15,7)decoder on Virtex 5 FX70TFF1136 requires 77 look-up tables (LUTs) with the maximum throughput reaching 1.7 Gbps.

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“…Step by step decoding algorithm [5] is used for this hardware design, which avoids inverse operation, calculating the coefficients of error location polynomial and searching the roots. Figure 2 shows the functional block diagram of the step-by-step decoding algorithm.…”

Section: A Fec Blockmentioning

confidence: 99%

“…Among the decoding steps, Berlekemp's algorithm [9] to determine the error locator polynomial and [5], t determinants are calculated using the syndromes. Zero Checker logic is used to check whether determinant values are zero or not to find out the error pattern [5]. The initial error pattern is saved in flip-flops.…”

Section: A Fec Blockmentioning

confidence: 99%

Design and Implementation of a Co-Processor for Providing Data Protection in Embedded Systems

Durga

Islam²,

Sachid³

et al.

2005 Annual IEEE India Conference - Indicon

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This paper presents the design and implementation of a Co-Processor (CP), which can provide the basic blocks for data protection in embedded systems. This Co-processor can be used for forward error correction, random number generation and hash generation. It performs forward error correction using BCH and Reed Muller algorithms, non-deterministic random number generation and hash generation using SHA-1 algorithm. This can be interfaced with any 16-bit processor using 6-bit address bus, control signals and interrupt pins. The co-processor is verified initially using Altera ACEX FPGAs along with complete system interface targeting to 50 MHz clock frequency. The design is carried out in 1.0 um CMOS standard cell technology and timing paths are verified with static timing analysis tool targeting 20ns clock period.

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A high-speed real-time binary BCH decoder

Cited by 17 publications

References 6 publications

Power line communication chip design with data error detecting/correcting and data encrypting/decrypting ability

Power line communication chip design with data error detecting/correcting and data encrypting/decrypting ability

A Low-Complexity and High-Throughput RTL Design of a BCH (15,7) Decoder

Design and Implementation of a Co-Processor for Providing Data Protection in Embedded Systems

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