A high speed programming scheme for multi-level NAND flash memory

Choi, Young-Joon; Suh, Kang-Deog; Koh, Yong-Nam; Park, Jong-Wook; Lee, Ki-Jong; Yunjin, Cho; Suh, Byung-Hoon

doi:10.1109/vlsic.1996.507758

Cited by 12 publications

(3 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For now, the multilevel characteristics of ferroelectric transistors are usually demonstrated by using the incremental step-pulse programming (ISPP) method, which is used in conventional NAND flash memories (9,21,(24)(25)(26)(27)(28). To realize multilevel characteristics using the ISPP method, voltage pulses with an increasing amplitude are applied to the device to tune the threshold voltage (V th ) of the device (24,(29)(30)(31). However, these methods are not optimized with the partial polarization switching characteristics of the ferroelectric layer; hence, the threshold voltage of the ferroelectric transistor shows a nonlinear relationship with increasing pulse amplitudes (32).…”

Section: Introductionmentioning

confidence: 99%

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Kim,

Lee

2024

Sci. Adv.

View full text Add to dashboard Cite

Ferroelectric transistors based on hafnia-based ferroelectrics exhibit tremendous potential as next-generation memories owing to their high-speed operation and low power consumption. Nevertheless, these transistors face limitations in terms of memory window, which directly affects their ability to support multilevel characteristics in memory devices. Furthermore, the absence of an efficient operational technique capable of achieving multilevel characteristics has hindered their development. To address these challenges, we present a gate stack engineering method and an efficient operational approach for ferroelectric transistors to achieve 16-level data per cell operation. By using the suggested engineering method, we demonstrate the attainment of a substantial memory window of 10 V without increasing the device area. Additionally, we propose a displacement current control method, facilitating one-shot programming to the desired state. Remarkably, we suggest the compatibility of these proposed methods with three-dimensional (3D) structures. This study underscores the potential of ferroelectric transistors for next-generation 3D memory applications.

show abstract

Section: Introductionmentioning

confidence: 99%

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Kim,

Lee

2024

Sci. Adv.

View full text Add to dashboard Cite

show abstract

“…Semiconductors have continually been developed to improve their density and performance. The conventional memory structure used to be 2D NAND flash; however, owing to structural limitations of being further scaled down, it was changed to 3D NAND flash memory [1][2][3][4][5][6]. However, the size of 3D NAND flash memory is also approaching its limit.…”

Section: Introductionmentioning

confidence: 99%

Channel Potential of Bandgap-Engineered Tunneling Oxide (BE-TOX) in Inhibited 3D NAND Flash Memory Strings

Cho,

Jung,

Kang

2024

Electronics

View full text Add to dashboard Cite

In this study, the channel potential of inhibited strings in 3D NAND flash memory using a bandgap-engineered tunneling oxide (BE-TOX) structure is analyzed. The equivalent oxide thickness (EOT) of the structure using BE-TOX was designed to be the same as the conventional 3D NAND flash memory, and the channel potentials of the down coupling phenomenon (DCP) and natural local self-boosting (NLSB) effect were analyzed. As a result, the BE-TOX structure was confirmed to have a higher channel potential in the DCP and NLSB than the conventional structure, making it relatively effective for program disturbance. The main reason for the difference in the channel potential between the BE-TOX and conventional structures is that adjacent cells have different threshold voltages (Vth). When the same program voltage (VPGM) and program time (TPGM) were applied during the program operation, Vth decreased in the BE-TOX structure, which increased the channel potential when DCP and NLSB occurred. Finally, a simulation was conducted by varying the thicknesses of the oxide and nitride in the BE-TOX structure. Despite the EOT being fixed and the thicknesses of both nitride and oxide being varied, the channel potential was affected.

show abstract

“…Semiconductor technology is pivotal in modern society, serving as an indispensable foundation across diverse fields. As the demand for semiconductors continues to surge, NAND flash memory technology and performance are constantly evolving, with innovations that encompass enhanced speed, increased density, and reduced power consumption [1][2][3][4][5][6][7][8][9]. Nevertheless, 2D NAND flash memory is continuously being replaced by 3D NAND flash memory due to technical obstacles such as limited cell density, interference, finite lifespan, and persistent downscaling challenges [10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory

Yun,

Lee,

Ryu

et al. 2024

Electronics

View full text Add to dashboard Cite

This paper proposes an optimized program operation method for ferroelectric NAND (FE-NAND) flash memory utilizing the gate-induced drain leakage (GIDL) program and validated through simulations. The program operation was performed by setting the time for the unselected cell to reach the pass voltage (Vpass) to 0.1 µs, 0.2 µs, and 0.3 µs, respectively. As the time for the unselected word line (WL) to reach Vpass increases, the channel potential increases due to a decrease in the electron–hole recombination rate. After the program operation, the threshold voltage (Vth) shift of the selected cell and the pass disturb of the unselected cells according to the Vpass condition were analyzed. Consequently, there was a more significant change in Vth among selected cells compared to the time for unselected cells to reach Vpass as 0.1 µs. The findings of this study suggest an optimal program operation that increases slowly and decreases rapidly through the variation of Vth according to the program operation. By performing the proposed program operation, we confirmed that low-power operation is achievable by reducing the WL voltage by 2 V and the bit line (BL) voltage by 1 V, in contrast to the conventional GIDL program.

show abstract

A high speed programming scheme for multi-level NAND flash memory

Cited by 12 publications

References 0 publications

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Channel Potential of Bandgap-Engineered Tunneling Oxide (BE-TOX) in Inhibited 3D NAND Flash Memory Strings

The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory

Contact Info

Product

Resources

About