A high speed power efficient dynamic comparator designed in 90nm CMOS technology

Sharma, Vijay; Sharma, Gaurav; Kumar, Divesh

doi:10.1109/ccintels.2015.7437942

2015 Communication, Control and Intelligent Systems (CCIS) 2015

DOI: 10.1109/ccintels.2015.7437942

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A high speed power efficient dynamic comparator designed in 90nm CMOS technology

Vijay Sharma

Gaurav Sharma

Divesh Kumar

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A high speed power efficient dynamic comparator designed in 90nm CMOS technology

Cited by 1 publication

References 8 publications

Low Power Latch Comparator - A Study

Low Power Latch Comparator - A Study

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