A high speed, low power PRML read channel device

Sonntag, J.; Agazzi, O.E.; Aziz, P.M.; Burger, H.; Comino, V.; Heimann, M.; Karanink, T.; Khoury, J.M.; Madine, S.; Nagaraj, K.; Offord, Glen E.; Peruzzi, Robert; Plany, J.; Rao, N. Bheema; Sayiner, N.; Setty, P.; Threadgill, K.

doi:10.1109/20.364805

Cited by 43 publications

(10 citation statements)

References 6 publications

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“…, the discrete-time model of the oversampled dibit response is (3) The SNR at the output of the channel is dB (4) Given an SNR, can be determined by performing simple algebraic manipulations on (4).…”

Section: Filter Design Proceduresmentioning

confidence: 99%

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A parallel architecture for multilevel decision feedback equalization

Kenney

Melas

1998

IEEE Trans. Magn.

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The data rate in a decision-feedback detector is limited by the critical timing loop. Within one clock cycle, the result of a decision by the comparator must be able to make its way back through the feedback filter and summing junction to reappear at the comparator input. It is shown here that multilevel decision feedback equalization (MDFE) can be readily modified to allow two clock cycles for the completion of this critical timing loop. This is accomplished by readjusting the forward equalizer until the first coefficient in the feedback filter is forced to zero. There is no significant degradation in performance in the application as a read/write channel for a hard disk drive. A parallel architecture can then be developed in which the entire structure is clocked at one half of the channel clock rate. A mixed analog/digital circuit topology is suggested for implementing this structure. A further proposal is that the feedback filter can be implemented as a set of small lookup tables, each pipelined to achieve highest data rate.

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Section: Filter Design Proceduresmentioning

confidence: 99%

“…Class IV partial response equalization followed by a maximum likelihood detector (PR4ML) has successfully replaced peak detectors in many current hard disk drive products [4], [5], [17]. In a linear channel dominated by additive white Gaussian noise, PR4ML clearly outperforms peak detection.…”

Section: Introductionmentioning

confidence: 99%

A parallel architecture for multilevel decision feedback equalization

Kenney

Melas

1998

IEEE Trans. Magn.

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“…9 a), an analog finite impulse response (FIR) equalizer, which processes sampled analog signals, is placed before the ADC. Implementations of this PRML architecture have been reported in [5] and [10]. The advantage of an analog FIR equalizer is that it avoids the enhancement of quantization noise.…”

Section: -1-3mentioning

confidence: 98%

“…In [10], a 10-tap analog, direct-form FIR equalizer was presented, where the analog samples are stored in sequentially addressed sample-and-hold circuits, and then accessed through a rotation switch matrix for the filtering operation. Digital FIR equalizer implementations used both the direct and transposed form, and high data rates were achieved with pipelining, parallelization, optimized bit-plane architectures, redundant number representation, distributed arithmetic, domino logic and self-timed data paths, while power and area were reduced by Booth encoding or device sizing [12]- [15].…”

Section: -1-4mentioning

confidence: 99%

“…The analog front-end includes a VGA, CTF, 10-tap analog FIR equalizer and flash ADC with a resolution of 5.75 bits in read mode. The FIR equalizer was designed using the architecture described in [10]. In the digital domain, the read channel comprises a 16-state Viterbi detector, a parity postprocessor, and circuits for the modulation and parity codes.…”

Section: VIIImentioning

confidence: 99%

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Digital signal processing in read channels

Haratsch¹,

Keirn²

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.

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Digital signal processing (DSP) has been a key technology in read channels, contributing significantly to the dramatic storage capacity and data rate growth of hard disk drives. This tutorial paper provides an overview of magnetic recording trends, and it discusses the DSP algorithms and architectures that have been employed in read channels for equalization, detection and coding. This paper also presents both a read channel and a hard disk drive SoC chip in 0.16 μm CMOS process.

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