2018
DOI: 10.1007/s10470-018-1183-8
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A high-speed, high-linearity, and energy-efficient subranging single-side capacitor switching scheme for SAR ADCs

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Cited by 7 publications
(3 citation statements)
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“…Te MSB capacitor is arranged as the conventional binary-weighted technique, while the next 9 bits are divided into two-stage subarray capacitors that replace the big-weight capacitors with 7 equal capacitors. Several works have adopted special arrangements for capacitor array technique [54][55][56][57][58][59][60][61]. Te asymmetric capacitors technique [54] is shown in Figure 17, where MSB on the higher side of the capacitor array is removed.…”
Section: Capacitive Dac Array (Cdac)mentioning
confidence: 99%
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“…Te MSB capacitor is arranged as the conventional binary-weighted technique, while the next 9 bits are divided into two-stage subarray capacitors that replace the big-weight capacitors with 7 equal capacitors. Several works have adopted special arrangements for capacitor array technique [54][55][56][57][58][59][60][61]. Te asymmetric capacitors technique [54] is shown in Figure 17, where MSB on the higher side of the capacitor array is removed.…”
Section: Capacitive Dac Array (Cdac)mentioning
confidence: 99%
“…In this technique, one more bit has been added as indicated in Figure 21. Te work [59] employs the subrange single-side technique to resolve the frst few bits. Tis helps the proposed single-side technique to detect and skip switching in the main stage.…”
Section: Capacitive Dac Array (Cdac)mentioning
confidence: 99%
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