A high-speed and low-power pipelined binary search analog to digital converter

Mesgarani, Ali; Tekin, Ahmet; Ay, Suat U.

doi:10.1109/mwscas.2011.6026343

Cited by 7 publications

(4 citation statements)

References 6 publications

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“…The proposed ADC is similar to an asynchronous SAR ADC [6,7,8,9,10,11,12], a pipelined ADC [1], a subranging ADC [1], or a binary-search ADC [28,29,30,31] in some aspects, but has several different points.…”

Section: Discussionmentioning

confidence: 99%

Asynchronous capacitive SAR ADC based on Hopfield network

Bai

Katayama

Yao

et al. 2022

IEICE Electron. Express

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This letter revisits a Hopfield network for an SAR ADC configuration, which enables low voltage, low power and fast operation with small circuitry. It employs an asymmetrical Hopfield network to avoid local minimum, and it uses capacitors and switches instead of very large resistors. Our N-bit SAR ADC uses N chopper-type comparators with asynchronous parallel operation, which is different from the conventional asynchronous SAR ADC employing only one comparator. It requires only the sampling clock for each input data sampling; no internal high frequency clock is required. Its AD conversion time is determined only by the comparator delays and the capacitor charge/discharge settling times; hence it is very fast and the AD conversion latency is only one or two clock cycles. Its operation is verified with SPICE simulations.

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Section: Discussionmentioning

confidence: 99%

Asynchronous capacitive SAR ADC based on Hopfield network

Bai

Katayama

Yao

et al. 2022

IEICE Electron. Express

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“…This yields to a figure of merit of 135fJ/conversion-step. The ADC achieves simpler timing and higher operating speed compared to the preceding ADC reported in [10].…”

Section: Track and Hold (Tha)mentioning

confidence: 99%

A 5-bit 1.25GS/s 4.7mW delay-based pipelined ADC in 65nm CMOS

Mesgarani

Yan

et al. 2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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This paper presents a delay based pipeline (DBP) analog to digital converter (ADC) suitable for high speed and low power applications. Active sample and hold and residue amplifier used in conventional pipeline ADCs are replaced by an analog delay line. The analog delay line is implemented by timeinterleaved sampling of the signal in each stage of the ADC. A novel multi-phase clock generator is introduced to generate ADC timing signals. A 5-bit, 1.25 GS/s DBP ADC is designed in 65nm CMOS process. Post-layout simulations confirm that the proposed ADC achieves a peak SNDR of 30.5dB while consuming 4.7mW from a single 1.2V power supply.

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“…Digital wireless communication applications, such as ultrawide band (UWB) and wireless personal area network (WPAN), cognitive and software defined radios etc., have lead to the increase in demand for low power, high speed analogto-digital converters (ADCs) with higher sampling rates [1], [2]. Traditionally, the flash ADCs were the preferred choice for such applications.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the high power consumption and large area overhead are the two main drawbacks of any flash type architecture of ADCs. On the other hand, Successive-Approximation-Register (SAR) ADCs are quite energy efficient, but they usually suffer from the problem of low speed of operation [1], [2]. Hence, the search for the ADC architecture which can provide a balance between the operational speed and the power consumption was obvious.…”

Section: Introductionmentioning

confidence: 99%

A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications

Mukherjee

Saha

Mostafa

et al. 2012

2012 International Symposium on Electronic System Design (ISED)

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In this paper the implementation of a low power high speed 4-bit Binary Search ADC (BS-ADC) is reported using 180 nm CMOS technology. The concept of Threshold Modified Comparator Circuit (TMCC) is introduced as a modification of the latch-based conventional comparators. The reported structure of the ADC occupies an active area of 0.0157 mm 2 and consumes 127 μW of average power while operating with an input frequency (f in ) of 5 MHZ, and a supply voltage of 1.8Volt. For this proposed architecture, the maximum sampling rate is obtained as 0.2 GSPS. At 0.2 GSPS sampling rate, the Signal to Noise plus Distortion Ratio (SNDR) is found to be 20.84 dB, yielding the Effective Number of Bits (ENOB) as 3.2 bit.

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A high-speed and low-power pipelined binary search analog to digital converter

Cited by 7 publications

References 6 publications

Asynchronous capacitive SAR ADC based on Hopfield network

Asynchronous capacitive SAR ADC based on Hopfield network

A 5-bit 1.25GS/s 4.7mW delay-based pipelined ADC in 65nm CMOS

A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications

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