A high-speech 32 bit IEEE floating-point chip set for digital signal processing

Abstract

A set of two VLSI circuits well-suited for digital signal processing is described which provides the complete 32 bit floating-point multiplier and adder functions. The data lorniat conforms with the new IEEE P754 standard. Operations include multiplication, add, subtract, conversion to and from 24 bit integer numbers and absolute value.Multiply and add times are both 600 nsec in a flow through manner. This is reduced to 200 nsec when operated in a three stage pipeline manner using internal registers. Both chips are fabricated in high-speed NMOS with 3 micron minimum feature size, which results in low power consumption of 1.5 watts typically. They are packaged in 64-pin dual-in-line package and 68-pin 1 eadi ess-chip-carrier. The applications of this chip set in FFT, digital filtering and array processing are described in this paper. * WTL1O32/WTL1O33 HARDWARE FOR FLOATING-POINTUp until now, the digital signal processing system designer has had -few attractive ways to use floatingpoint processing. Commercially available array processors are expensive. They are either of coprocessor type like INTEL 8087, which is too slow, or special purpose processor type which is bulky and power hungry. WTL1O32/1033 handle the floating-point data path components necessary for the 32 bit IEEE standard in high density, low power NMOS with the speed, architecture and control mechanisms so that they can be used in highspeed real-time signal processors. (1) A NEW VLSI CHIP SET A common block diagram for the two VLSI chips is shown in Figure 1. For the floating-point multiplier the array is a significand multiplier and exponent adder. For the floating-point ALU the array is a denormalizer, significand adder and re-normalizer. Both have the same register structure and pinouts so that loading and unloading of data, function, modes of operation and status are uniform. As the figure shows, the array can be divided into three additional stages separated by registers so that data can be pipelined through, in effect tripling the speed.16.6.1The function codes are also pipelined such that the data flow can continue even when the function is changing. Input and outputAll inputs and outputs, both data and control, are fully registered on the chip. These along with three-state outputs make for ease of use in bu oriented systems. The two 32 bit input operands and the output result are time multiplexed through 15 pins so that standard 54 and 68 pin packages could be used. Inputs and ouputs can be clocked at twice the pipe-lined rate so this timesharing is invisible. The loading and unloading of the array is controlled by separate registers where the output, like the function control, is pipelined so it remains with the pertinent data. The input operands can be loaded individually so if one remains constant bus traffic is reduced. Modes of operationThe IEEE standard specifies not only the floating-point format but the detection and treatment of exceptions (such as underflow) and choices in the procedure for rounding and representation of infinity. A...