A High Precision Time-to-Digital Converter based on Multi-chain Interpolation with a Low Cost Artix-7 FPGA

Wang, Junchen.; Feng, C. Q.; Dong, Wenhao; Shen, Zuojun; Liu, Shubin

doi:10.1109/ebccsp53293.2021.9502368

Cited by 7 publications

(3 citation statements)

References 10 publications

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“…Given that we are working to develop a timing measurement system with picosecond resolution, even the minute variations in the physical distances between any two-carry logic (CARRY4) blocks in the WU-A architecture will lead to high non-linearity. Therefore, a bin-by-bin calibration is necessary [ 40 ]. This part of the calibration using data processing is performed with an automatic calibration method.…”

Section: Methodsmentioning

confidence: 99%

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method

Alshahry,

Alshehry,

Alhazmi

et al. 2023

Sensors

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We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost Field-Programmable Gate Array (FPGA), Artix-7, from Xilinx. Compared to prior works, our high-precision multi-channel TDC has the lowest SWaP-C requirements. We demonstrate an average time precision of less than 3 ps and a Root Mean Square resolution of about 1.81 ps. We propose a novel Wave Union type A architecture where only the first multiplexer is used to generate the wave union pulse train at the arrival of the start signal to minimize the required computational processing. In addition, an auto-calibration algorithm is proposed to help improve the TDC performance by improving the TDC Differential Non-Linearity and Integral Non-Linearity.

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Section: Methodsmentioning

confidence: 99%

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method

Alshahry,

Alshehry,

Alhazmi

et al. 2023

Sensors

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show abstract

“…Output signal Input signal Delay parameter The focus of the delay generator designed in this article is a time method (structure) called a carry delay chain [10][11][12], which is mainly used in various delay systems and time interval measurement systems, and it is currently used more frequently as a time method. In the field of time interval measurement, this time method is also called delay line interpolation [13][14][15]. The carry delay chain is mainly implemented in a FPGA or an ASIC, which have high degrees of integration.…”

Section: Delay Generatormentioning

confidence: 99%

A Picosecond Delay Generator Optimized by Layout and Routing Based on FPGA

Zhu

Tang

et al. 2023

Sensors

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A delay generator is a timing control device that can generate a delay for the input signal according to the actual requirements. A delay generator with a combination of rough delay and precise delay is implemented on a Xilinx Kintex-7 series FPGA with a design scheme based on carry delay chain. The delay generator uses the delay time parameters sent by the upper monitor to work and to reflect the current working state to the upper monitor. In this article, a theoretical model of the delay generator is designed, and a delay compensation scheme is proposed to make the working state of the theoretical model closer to the actual circuit. Through simulation experiments, the time resolution of the delay generator is 54 ps, and the time accuracy is less than 50 ps. The delay scheme adopted in this article is highly scalable, and the time resolution and time accuracy can be further improved. Finally, a theoretical model of the delay generator with relatively high time resolution is implemented through low resource occupancy rate and little workload.

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“…It is implemented on the xc7a35tcsg324-1 Artix-7 FPGA board. Artix-7 [11], [12] is a development platform designed around the Xilinx in-situ programmable gate array. It is designed entirely for use as a MicroBlaze softcore processor system.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of SIMON-128 Cryptographic Algorithm Using Artix-7

Ghayoula¹,

Fattahi²,

Smida³

et al. 2023

Preprint

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FPGA is a hardware architecture based on a matrix of programmable and configurable logic circuits thanks to which a large number of functionalities inside the device can be modified using a hardware description language. These functionalities must often be secured especially when the context is sensitive (military, banking, medical, legal, etc.). In this paper, we put forward an efficient implementation of SIMON's block cipher algorithm using Xilinx Vivado 2018.2. The proposed design is analyzed through simulation on Xilinx Artix-7. A prototype of our design is implemented using the xc7a35tcsg324-1 FPGA chip. Performance and results are discussed.

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A High Precision Time-to-Digital Converter based on Multi-chain Interpolation with a Low Cost Artix-7 FPGA

Cited by 7 publications

References 10 publications

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method

A Picosecond Delay Generator Optimized by Layout and Routing Based on FPGA

FPGA Implementation of SIMON-128 Cryptographic Algorithm Using Artix-7

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