A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCs

Pandey, Jai Gopal; Goel, Tarun; Nayak, Mausam; Mitharwal, Chhavi; Karmakar, Arindam; Singh, R. B.

doi:10.1109/socc.2018.8618487

Cited by 5 publications

(6 citation statements)

References 13 publications

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“…Output of the bridge apbo uses apb_slv_out_type record type signal. The bridge's input apbi arrives from the IP core and works with apb_slv_in_type record type signal as per Pandey et al (2018b) and by Gaisler et al (2010). The complete design is targeted for Xilinx ML-507 FPGA platform.…”

Section: Comparison With Existing Asic Implementations At 180 Nm Cmos...mentioning

confidence: 99%

“…The architecture, when implemented in a 180 nm ASIC, requires 39.98 k gates and provides 3,840 Mbps of throughput. A report on performance metrics for a set of lightweight block ciphers is given by Kerckhof et al (2012) The design is implemented in four metal layer SCL 180 nm CMOS technology semi-conductor laboratory (SCL), (which is a TowerJazz enabled foundry), consumes 69,092 GE and 1.85 mm 2 chip area Pandey et al (2018b). Recently, an integrated design for the AES and PRESENT cipher realization in an SoC environment is presented by Pandey et al (2020).…”

Section: Introductionmentioning

confidence: 99%

“…A report on performance metrics for a set of lightweight block ciphers is given by Kerckhof et al (2012). Some recent FPGA implementations of the PRESENT cipher include Lara-Nino et al (2016a, 2016b); Pandey et al (2018a); and Pandey et al (2018b). In the design of Pandey et al (2018a), Xilinx Virtex-5 xc5vfx70t FPGA device is used to synthesize the PRESENT encryption/decryption core.…”

Section: Introductionmentioning

confidence: 99%

“…In the design of Pandey et al (2018a), Xilinx Virtex-5 xc5vfx70t FPGA device is used to synthesize the PRESENT encryption/decryption core. The design of Pandey et al (2018b) has used 84 FPGA slices on the Xilinx Virtex-5 xc5vlx50 device. The design is implemented in four metal layer SCL 180 nm CMOS technology semi-conductor laboratory (SCL), (which is a TowerJazz enabled foundry), consumes 69,092 GE and 1.85 mm 2 chip area Pandey et al (2018b).…”

Section: Introductionmentioning

confidence: 99%

“…The design of Pandey et al (2018b) has used 84 FPGA slices on the Xilinx Virtex-5 xc5vlx50 device. The design is implemented in four metal layer SCL 180 nm CMOS technology semi-conductor laboratory (SCL), (which is a TowerJazz enabled foundry), consumes 69,092 GE and 1.85 mm 2 chip area Pandey et al (2018b). Recently, an integrated design for the AES and PRESENT cipher realization in an SoC environment is presented by Pandey et al (2020).…”

Section: Introductionmentioning

confidence: 99%

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Design, integration and implementation of crypto cores in an SoC environment

Pandey

Gupta

Karmakar

2022

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Purpose The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations. Design/methodology/approach An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided. Findings FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed. Originality/value The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

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Section: Comparison With Existing Asic Implementations At 180 Nm Cmos...mentioning

confidence: 99%