A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding

Kao, Yu-Chien; Kuo, Huang-Chih; Lin, Yi; Hou, Chia-Wen; Li, Yi-Hsien; Huang, Hao-Tin; Lin, Youn-Long

doi:10.1109/apccas.2006.342532

Cited by 13 publications

(14 citation statements)

References 4 publications

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“…Although the proposed 16-pixel parallel architecture with block-level/mode-level co-reordering approach consumes a larger area cost, the hardware utilization or our work is relatively higher than that of previous works. As can be seen in TABLE III, our architecture is 7.3x, 2.8x and 4.2x faster than 2.3x, 1.4x and 2.8x larger than that of [3], [5] and [7], respectively. The area of intra 4x4 prediction architecture of our work, which is fully optimized, is only about 1/5th, 1/8th and 1/4th of that of [3], [5] and [7].…”

Section: Resultsmentioning

confidence: 84%

“…As can be seen in TABLE III, our architecture is 7.3x, 2.8x and 4.2x faster than 2.3x, 1.4x and 2.8x larger than that of [3], [5] and [7], respectively. The area of intra 4x4 prediction architecture of our work, which is fully optimized, is only about 1/5th, 1/8th and 1/4th of that of [3], [5] and [7]. And there is still some room for the optimization of our architecture for intra 16x16/chroma prediction.…”

Section: Resultsmentioning

confidence: 84%

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A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder

Ren

Fan

Chen

et al. 2012

17th Asia and South Pacific Design Automation Conference

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Intra prediction is the most important technology in H.264/AVC intra frame encoder. But there is extremely complicated data dependency and an immense amount of computation in intra prediction process. In order to meet the requirements of real-time coding and avoid hardware waste, this paper presents a parallel and high efficient H.264/AVC intra prediction architecture which targets high-resolution (e.g. 4kx2k) video encoding applications. In this architecture, the optimized intra 4x4 prediction engine can process sixteen pixels in parallel at a slightly higher hardware cost (compared to the previous four-pixel parallel architecture). The intra 16x16 prediction engine works in parallel with intra 4x4 prediction engine. It reuses the adder-tree of Sum of Absolute Transformed Difference (SATD) generator. Moreover, in order to reduce the data-dependency in intra 4x4 reconstruction loop, a block-level and mode-level co-reordering strategy is proposed. Therefore, the performance bottleneck of H.264/AVC intra encoding can be alleviated to a great extent. The proposed architecture supports full-mode intra prediction for H.264/AVC baseline, main and extended profiles. It takes only 163 cycles to complete the intra prediction process of one macroblock (MB). This design is synthesized with a library. The result shows that it takes 61k gates and can run at 215MHz, supporting real-time encoding of 4kx2k@40fps video sequences.

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Section: Resultsmentioning

confidence: 84%

Section: Resultsmentioning

confidence: 84%

A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder

Ren

Fan

Chen

et al. 2012

17th Asia and South Pacific Design Automation Conference

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“…Since 2005, numerous papers, patents, and books about H.264/AVC have been published because of its high compression performance. A lot of previous works have proposed highperformance hardware architectures for each functional modules such as the intra prediction unit [55], [84], [88], [90], [93], transform and quantization unit [19], [74], [85], and entropy coding unit [14], [27], [65] in an H.264/AVC encoder. All of these works achieve superior performance because they optimize the performance of each unit without considering the integration issues.…”

Section: Related Workmentioning

confidence: 99%

VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding

Kuo

Lin

2013

IPSJ Transactions on System LSI Design Methodology

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Intra-frame encoding is useful for many video applications such as security surveillance, digital cinema, and video conferencing because it supports random access to every video frame for easy editing and has low computational complexity that results in low hardware cost. H.264/AVC, which is the most popular video coding standard today, also defines novel intra-coding tools to achieve high compression performance at the expense of significantly increased computational complexity. We present a VLSI design for H.264/AVC intra-frame encoder. The paper summaries several novel approaches to alleviate the performance bottleneck caused by the long data dependency loop among 4 × 4 luma blocks, integrate a high-performance hardwired CABAC entropy encoder, and apply a clock-gating technique to reduce power consumption. Synthesized with a TSMC 130 nm CMOS cell library, our design requires 194.1 K gates at 108 MHz and consumes 19.8 mW to encode 1080p (1920 × 1088) video sequences at 30 frames per second (fps). It also delivers the same video quality as the H.264/AVC reference software. We suggest a figure of merit called Design Efficiency for fair comparison of different works. Experimental results show that the proposed design is more efficient than prior arts.

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“…Not all of the algorithms explained above are suitable for hardware implementation which requires a relatively regular computation structure. Thus, a number of studies have been published on the algorithms and architecture for the hardware implementation of intrapredictions [1,4,[27][28][29]. In [4], the DC components of 4 × 4 DCT coefficients are precalculated when 16 × 16 intraprediction is performed.…”

Section: Introductionmentioning

confidence: 99%

“…This technique enables pipelining of transform and quantization (TQ) and inverse quantization and inverse transform (IQIT) of the results from 16 × 16 intraprediction. In [27,28], an effective architecture is suggested for intraprediction and mode decision. For these hardware implementations, the hardware resources for 4 × 4 intraprediction and reconstruction are often idle and wasted.…”

Section: Introductionmentioning

confidence: 99%

Early Termination and Pipelining for Hardware Implementation of Fast H.264 Intraprediction Targeting Mobile HD Applications

Jung

Jin

Lee

2008

EURASIP J. Adv. Signal Process.

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Recommended by Liang-Gee Chen H.264/AVC adopts aggressive compression algorithms at the cost of increased computational complexity. To speed up the H.264/AVC intraframe coding, this paper proposes two novel techniques: early termination and pipelined execution. In P slices, intra 4 × 4 and 16× 16 predictions are early terminated with the threshold determined by the cost of motion estimation. In I slices, intra 4×4 prediction is early terminated with the threshold derived from intra 16×16 prediction. The threshold function is chosen as a monotonically decreasing linear function with its optimal coefficients determined by experiments. For the pipelined execution of 4×4 intrapredictions, the processing order of 4×4 blocks is changed to reduce the dependencies between consecutively processed blocks. In I slices, computation for 4 × 4 intraprediction is reduced by 19 percent with the proposed early termination. In P slices, computations for 4 × 4 and 16 × 16 intrapredictions are reduced by more than 81 and 91 percents, respectively. The pipelined execution reduces the computation time by 41 percent. In spite of the speed-up by the proposed methods, degradation in ratedistortion performance is negligible. The proposed pipelined execution is integrated with other H.264/AVC hardware accelerators and fabricated as an SoC using Dongbu 0.13 μm technology.

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A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding

Abstract: We propose a high-performance hardware accelerator for intra prediction and mode decision in H.264/AVC video encoding. We use two intra prediction units to increase the performance.

Cited by 13 publications

References 4 publications

A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder

A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder

VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding

Early Termination and Pipelining for Hardware Implementation of Fast H.264 Intraprediction Targeting Mobile HD Applications

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A High-Performance VLSI Architecture for Intra Prediction and Mode Decision in H.264/AVC Video Encoding

Abstract: We propose a high-performance hardware accelerator for intra prediction and mode decision in H.264/AVC video encoding. We use two intra prediction units to increase the performance.

Cited by 13 publications

References 4 publications

A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k&#x00D7;2k H.264/AVC video encoder

A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k&#x00D7;2k H.264/AVC video encoder

VLSI Architecture Design for H.264/AVC Intra-frame Video Encoding

Early Termination and Pipelining for Hardware Implementation of Fast H.264 Intraprediction Targeting Mobile HD Applications

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A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder

A 16-pixel parallel architecture with block-level/mode-level co-reordering approach for intra prediction in 4k×2k H.264/AVC video encoder