A High-Performance On-Chip Bus (MSBUS) Design and Verification

Abstract

This brief proposes a high-performance system-on-chip bus protocol termed the master-slave bus (MSBUS). Considering the inevitable tradeoff among area, throughput and energy efficiency, the control bus is developed as a low-cost and low-power bus, and the data bus is created as a high-throughput full-duplex bus with the feature of block data transfer. To evaluate the bus performance, we create four analytical models including transfer time consumption (TC), wire efficiency (WE), valid data bandwidth (VDB) and dynamic energy efficiency. Then, the advanced high-performance bus-, advanced eXensible interface (AXI)-, and MSBUS-based direct memory access (DMA) are developed as a case study of hardware implementation. It is observed that MSBUS DMA costs less hardware resources and achieves higher performance, especially in the block transfer mode. For instance, the results from both the analytical models and the practical tests show that the TC of MSBUS is close to 63% of the AXI, the WE and VDB of MSBUS are almost 2.3 and 1.6 times of the AXI respectively, and the energy consumption is half of AXI in the block transfer mode.Index Terms-Dynamic energy efficiency, system-on-chip (SoC), valid data bandwidth (VDB), wire efficiency (WE).

Hierarchical Synthesis of Approximate Multiplier Design for Field-programmable Gate Arrays (FPGA)-CSRmesh System

“…These works focused on the subcomponent designs, however, the impact of the approximations on structural implementations has not been considered. In most of the applications, the improvement on system-level has a greater potential to improve the circuit and system performance [25] [24] [22]. The implementation of multipliers usually has three steps: partial product configuration, product accumulation, and the bit shifters.…”

Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure

“…MBUS is defined as a control bus for functional register configuration [10]. Considering the instruction operations on energy-limited chips, MBUS is created for minimal power consumption and reduced interface complexity so that it only supports single transfer mode with at least one-cycle command and one-cycle data.…”

“…They are designed for a broad range of various applications and are characterized by high flexibility, scalability, and universality. Under this context, a cost-effective and power-efficient control bus named as master bus (MBUS) [10] has been proposed for specific IoT applications as our previous work, making a better balance between the limited energy on tiny-size embedded chips and high speed requirement of complex computations. Furthermore, it has been improved in [11] to preselect data sequence for Advanced Encryption Standard (AES) engines, so that the state buffering and rescheduling overhead can be reduced.…”

A Compression Algorithm Design and Simulation for Processing Large Volumes of Data from Wireless Sensor Networks

“…In order to reduce the power associated while transmission various compression schemes such as K-RLE [4], Adaptive Huffman coding [5] and many more [6], in this paper we implement the compression algorithm using a low-cost system-on-chip (SoC) architecture proposed in [7,8].…”