A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism

Abstract

SUMMARYSorting is an extremely important computation kernel that has been accelerated in a lot of fields such as databases, image processing, and genome analysis. Given that advent of Internet of Things (IoT) era due to mobile technology progressions, the future needs a sorting method that is available on any environment, such as not only high performance systems like servers but also low computational performance machines like embedded systems. In this paper, we present an FPGA-based sorting accelerator combining Sorting Network and Merge Sorter Tree, which is customizable by means of tuning design parameters. The proposed FPGA accelerator sorts data sent from a host PC via the PCIe bus, and sends back the fully sorted data sequence to it. We also present a detailed analytical model that accurately estimates the sorting performance. Due to these characteristics, designers can know how fast a developed sorting hardware is in advance and can implement the best one to fulfill the cost and performance constraints. Our experiments show that the proposed hardware achieves up to 19.5x sorting performance, compared with Intel Core i7-3770K operating at 3.50GHz, when sorting 256M 32-bits integer elements. However, this result is limited because of insufficient memory bandwidth. To overcome this problem, we propose a data compression mechanism and the experimental result shows that the sorting hardware with it achieves almost 90% of the estimated performance, while the hardware without it does about 60%. In order to allow every designer to easily and freely use this accelerator, the RTL source code is released as open-source hardware.

A Survey of Network-Based Hardware Accelerators

“…It has been shown that although very appreciable results have already been achieved, with various authors proving the benefits of reconfigurable hardware implemen-tations compared to software solutions, more work is still required in particular in the scope of exploring high-level synthesis potential and reducing the communication bottleneck, which is currently the main limiting factor of the majority of the designs. Different proposals have been carried out to mitigate the bandwidth limitation, such as communication-time data processing [32] and a data compression mechanism [51].…”

DPTC—An FPGA-Based Trace Compression

“…A common approach is the calculation of differences between values [16], [17], [18], [19], [20]. These differences may be between sampled data and a model [16] or between sampled data and a reference value (base) [17], [18] or between consecutive samples [16], [18], [19]. When dealing with signal traces, which are sampled at rates high enough that consecutive samples have values close to each other, i.e.…”

“…closer to zero, with shorter sequences. This approach is quite similar to the one presented in [18], where one sample works as base value and the following three samples undergo the differencing treatment. The base value can be chosen arbitrarily.…”

“…In some cases, through a pre-processing of the incoming data, a more advantageous probability distribution can be exploited. A common approach is the calculation of differences between values [16], [17], [18], [19], [20]. These differences may be between sampled data and a model [16] or between sampled data and a reference value (base) [17], [18] or between consecutive samples [16], [18], [19].…”

Design of FPGA-Based LZ77 Compressor With Runtime Configurable Compression Ratio and Throughput

“…The hardware acceleration technique is a method used to reduce the computational load of a system. This technique migrates some or all of the tasks that the CPU has performed to a hardware device such as a GPU [16], an ASIC [17], or an FPGA [17]- [23]. Some previous researches studied compression acceleration techniques and achieved high bandwidth by parallelizing frequently performed operations [20]- [22].…”