A High-Performance FPGA-Based Image Feature Detector and Matcher Based on the FAST and BRIEF Algorithms

Abstract

Image feature detection and matching is a fundamental operation in image processing. As the detected and matched features are used as input data for high-level computer vision algorithms, the matching accuracy directly influences the quality of the results of the whole computer vision system. Moreover, as the algorithms are frequently used as a part of a real-time processing pipeline, the speed at which the input image data are handled is also a concern. The paper proposes an embedded system architecture for feature detection and matching. The architecture implements the FAST feature detector and the BRIEF feature descriptor and is capable of establishing key point correspondences in the input image data stream coming from either an external sensor or memory at a speed of hundreds of frames per second, so that it can cope with most demanding applications. Moreover, the proposed design is highly flexible and configurable, and facilitates the trade-off between the processing speed and programmable logic resource utilization. All the designed hardware blocks are designed to use standard, widely adopted hardware interfaces based on the AMBA AXI4 interface protocol and are connected using an underlying direct memory access (DMA) architecture, enabling bottleneckfree inter-component data transfers.

On-Board Detection and Matching of Feature Points

“…As seen from Table 4, the maximal utilization is LUTs, which is about 43%, while only 19% in [39]. The minimal utilization is BRAMs, which is about 0%, while increases to 27% and 28% in [22,39], respectively. The utilization of DSPs is 59% in [22], while are 0 in [39] and this work.…”

“…In addition, the speedup of the proposed method is most significant. The reasons why the fps of the proposed method is lower than the [39] are that (1) In detection phase, the SURF detector is more time-consuming than FAST detector; (2) The image column in this paper is larger than the image column of [39]. The larger column will take more time in operation on FPGA.…”

“…The minimal utilization is BRAMs, which is about 0%, while increases to 27% and 28% in [22,39], respectively. The utilization of DSPs is 59% in [22], while are 0 in [39] and this work. Furthermore, the FPGA resource of this work will reduce when the whole system is further optimized.…”

“…If the clock frequency is defined as 100 MHz, the fps can't achieve 356. The FAST + BRIEF [39] reach 325 fps, while the clock frequency is only 100 MHz. The proposed method reaches 304 fps with the same clock frequency as [39].…”

“…The FAST + BRIEF [39] reach 325 fps, while the clock frequency is only 100 MHz. The proposed method reaches 304 fps with the same clock frequency as [39]. In addition, the speedup of the proposed method is most significant.…”