Abstract:A new high-performance architecture for decoding the irregular Low-Density Parity-Check (LDPC) codes with respect to the iterative message-passing decoding algorithm is explored. The proposed method is based on reducing the logic delays in the iterative processing of the bit nodes and check nodes leading to the increment of maximum possible frequency. The simulations show the efficiency of the proposed method in low/high-complexity graph matrices, though it is more effective in highcomplexity ones. About 28% r… Show more
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