A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design

Liu, Zhongyang; Zhang, Haineng; Jiang, Jianwei; Jia, Yanjie; Xie, Yuqiao; Zou, Shichang; Zhang, Zhengxuan

doi:10.1109/tvlsi.2022.3204827

Cited by 13 publications

(8 citation statements)

References 26 publications

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“…Figure 3-(b) shows the schematic of SHLR [20], which consists of two CG-based 2-input CEs and three input-splitting inverters, forming feedback interlocking loops to recover the original values after a radiation event. An SHLR latch can tolerate and [20], (c) HLDTL-EV [21], (d) DNUSH [22], (e) TNULH [13], (f) TNURL [14], (g) QNUTL [15], (h) Quad-SIRI [16], (i) HLMR [17] and (j) LCQNUSR [18]. self-recover from SNU.…”

Section: Previous Radiation Hardened Latchesmentioning

confidence: 99%

“…Figure 3-(i) shows the schematic of HLMR [17], which is composed of eight 2-input CEs and eight CG-based 2-input CEs to form many feedback loops with 16 redundant nodes. Eight TGs are used to initialize the values of internal nodes.…”

Section: Previous Radiation Hardened Latchesmentioning

confidence: 99%

“…Therefore, in order to provide highly reliable integrated circuits, it is necessary to design storage cells that can tolerate and even recover from MNU. To provide radiation hardening capability, researchers have proposed a series of radiation-hardened circuit structures [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22]. Some of them use time redundancy, e.g., using delay elements as error-filterable components [8], some use pulse detection technology, such as that in [9], and some use space redundancy, e.g., introducing redundant storage nodes and/or triple-moduleredundancy (TMR) along with voting circuits [10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

“…In recent years, with the exploration of deep space, there are more and more cases of MNU, and the demand for a latch that can provide complete MNU self-recoverability is greatly increased [2,6]. In the 22nm SRAM, the ratio of the total number of MNU to the total number of SNU is as high as 50%, indicating that the influence of MNU is more severe [17]. Although there are many existing radiation-hardened latches, most of them can tolerate only a few node upsets, among which SNU and DNU tolerable latches are the main ones.…”

Section: Introductionmentioning

confidence: 99%

“…To the best of our knowledge, only a few latches can completely self-recover from QNU. Although few latches, such as those in [15][16][17], can completely tolerate QNU, they cannot completely self-recover from QNU.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

Yan,

Zhou,

Wei

et al. 2023

2023 IEEE International Test Conference in Asia (ITC-Asia)

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As CMOS processes continue to shrink, nano-scale CMOS latches have become increasingly sensitive to multiplenode upset (MNU) errors caused by radiation. To tolerate MNU, a novel quadruple-node-upset (QNU) self-recoverable latch is proposed in this paper. The proposed latch is mainly constructed from six blocks of three-level C-elements (TLCEs) and six inverters. With the mutual feedback of the various TLCEs, the proposed latch can recover from any QNU. Furthermore, due to the clock gating methodology and a highspeed transmission path, the proposed latch has lower overhead in terms of power dissipation and transmission delay. Simulation results show that the proposed latch achieves high reliability with moderate overhead compared to typical existing latches.

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Section: Previous Radiation Hardened Latchesmentioning

confidence: 99%

Section: Previous Radiation Hardened Latchesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

Yan,

Zhou,

Wei

et al. 2023

2023 IEEE International Test Conference in Asia (ITC-Asia)

View full text Add to dashboard Cite

show abstract

High‐precision single‐event transient hardened comparator with the sensitive node transient detection feedback latch technique

Xie,

Xu,

Liu

et al. 2024

Circuit Theory & Apps

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This paper comprehensively perfects the sensitive node transient detection feedback latch (SNTDFL) technique, subsequently conceptualizes an ideal hardening structure for the pre‐amplification stage, and proposes a radiation hardened by design (RHBD) strategy to cope with the severe single‐event transient (SET) effects of high‐precision voltage comparators in a space radiation environment. Analysis and verification results show that the hardening strategy exhibits excellent SET hardening performance, which can not only detect extremely small transient voltage disturbances at sensitive nodes but also effectively resist transient current pulses of various intensities generated by SETs. Compared with an unhardened high‐precision comparator, the proposed one, hardened with a hybrid strategy of SNTDFL and triple modular redundancy (TMR) techniques, can greatly preserve the original electrical properties and remarkably improve the tolerance of SET with little overhead. In addition, the proposed high‐precision comparator significantly reduces static power consumption compared with the one hardened with the TMR technique alone and has a smaller area overhead.

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A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements

Xu,

Tang,

et al. 2024

Microelectronics Journal

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A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design

Cited by 13 publications

References 26 publications

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation Hardness

High‐precision single‐event transient hardened comparator with the sensitive node transient detection feedback latch technique

A cost-effective and highly robust triple-node-upset self-recoverable latch design based on dual-output C-elements

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