A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher

Pandey, Jai Gopal; Goel, Tarun; Karmakar, Arindam

doi:10.1109/vlsid.2018.96

Cited by 18 publications

(12 citation statements)

References 11 publications

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“…The sender did not need to send a simple key but the storage coordinates of the key matrix and the receiver obtained the key from the matrix according to the coordinates, which effectively improves the security of key transmission. Pandey et al [9] proposed a Very Large Scale Integration (VLSI) architecture, with high performance and a limited area of 64-bit data path for lightweight cipher PRESENT, which realized high throughput rate and low power consumption on FPGA. For meeting the security requirements of different application environments, different algorithms are required for the encryption and decryption system to process data.…”

Section: Related Workmentioning

confidence: 99%

“…In the process of IoT data transmission, cryptographic algorithms are the most commonly effective means to guarantee data security [7,8,9]. The data volumes expansion and the IoT commoditization give computer hardware higher requirements for the speed, power consumption, and cost.…”

Section: Introductionmentioning

confidence: 99%

“…It has the advantages of fast processing speed, rich functions, high flexibility, and ultra-low power consumption. In recent years, FPGA has become an ideal platform for IoT to cope with big data and cloud computing [9].…”

Section: Introductionmentioning

confidence: 99%

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Dynamically Reconfigurable Encryption and Decryption System Design for the Internet of Things Information Security

Wang

Yao

Tong

et al. 2019

Sensors

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Information security is the foundation for building trust between the Internet of Things (IoT) and its users. Due to the sharp increase of information quantity and the limitation of hardware resources, it is difficult to maintain the high performance of hardware equipment, while also enhancing information security. To solve the problem of high consumption and low flexibility of multiple cryptographic algorithms hardware implementation, we have designed the Dynamically Reconfigurable Encryption and Decryption System, which is based on Field Programmable Gate Array. Considering the functional requirements, the cryptographic algorithm reconfigurable module files stored in External Memory could be configured dynamically into the assigned on-chip Reconfigurable Partition, supported by Core Controller and the Reconfiguration Control Platform. The experiment results show that, compared with the Static Encryption and Decryption System, our design reduces the logic resources by more than 30% and completes the algorithm swapping at the configuration speed of 15,759.51 Bytes/ms. It indicates that our design could reduce logic resources consumption and improve utilization efficiency and system flexibility.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Dynamically Reconfigurable Encryption and Decryption System Design for the Internet of Things Information Security

Wang

Yao

Tong

et al. 2019

Sensors

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“…To perform both encryption and decryption operations, FPGA implementations have been provided in [23, 28, 29]. In the implementation of [23], Spartan‐III FPGA has been used for encryption/decryption operations.…”

Section: Related Workmentioning

confidence: 99%

Hardware architectures for PRESENT block cipher and their FPGA implementations

Pandey

Goel

Karmakar

2019

IET Circuits, Devices & Systems

Self Cite

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Data security is essential for the proliferation of the Internet of things and cyber-physical system technologies. Data security can be efficiently achieved by incorporating lightweight cryptography techniques. In this study, a set of highperformance hardware architectures for PRESENT lightweight block cipher are proposed that perform encryption, decryption and integrated encryption/decryption operations. Datapath of the architectures is of 64 bit width that supports standard 80 and 128 bits key lengths. The architectures are synthesised on Xilinx Virtex-5 XC5VLX110T (ff1136-1) field-programmable gate array device of ML-505 platform. To perform functional verification, a large number of test vectors are used. Performance measurement is performed by evaluating maximum frequency, throughput, power dissipation and energy consumption. Experimentally, it is found that the proposed architectures are resource-efficient, high-performance and suitable for lightweight, latency-critical and low-power applications in comparison with existing architectures.

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“…In recent years, several FPGA-based implementations of the HIGHT and PRESENT algorithms have been reported in the literature [11][12][13][14][15][16][17][18][19][20][21]. For example, the first lightweight implementations of the block ciphers HIGHT and PRESENT on FPGA are presented in [11].…”

Section: Introductionmentioning

confidence: 99%

Efficient and high‐throughput application‐specific integrated circuit implementations of HIGHT and PRESENT block ciphers

Rashidi

2019

IET Circuits, Devices & Systems

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In this study, low-cost and high-throughput hardware implementations of the HIGHT (HIGh security and lightweigHT) and PRESENT lightweight block ciphers are presented. One of the most complex blocks in the HIGHT algorithm is addition modulo 2 8. In the proposed structure for implementation of this modular adder, the authors used the structure of Ladner-Fischer, Han-Carlson, Kogge-Stone and Sklansky adders, which are parallel prefix adders with low critical path delay and suitable hardware resources. In the PRESENT block cipher, for two key lengths 80-bit and 128-bit, the S-box is implemented based on an area-optimised combinational logic circuit. In the proposed S-box structure, the number of logic gates and critical path delay is reduced by using Karnaugh mapping and further factorisation. Also, to reduce the latency and increase throughput, the loop unrolling technique is applied in the structures. Implementation results of the proposed architectures in 180 nm complementary metal-oxide-semiconductor technology for different unroll factors are achieved. The results show improvements in terms of execution time, throughput and throughput/area compared to other related works.

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A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher

Cited by 18 publications

References 11 publications

Dynamically Reconfigurable Encryption and Decryption System Design for the Internet of Things Information Security

Dynamically Reconfigurable Encryption and Decryption System Design for the Internet of Things Information Security

Hardware architectures for PRESENT block cipher and their FPGA implementations

Efficient and high‐throughput application‐specific integrated circuit implementations of HIGHT and PRESENT block ciphers

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