A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

Smeys, P.; McGahay, V.; Yang, Insoon; Adkisson, J.; Beyer, Kevin; Bula, O.; Chen, Z.; Chu, Baojin; Culp, J.; Das, Sanghamitra; Eckert, Andrew R.; Hadel, L. M.; Hargrove, M.; Herman, J.; Lin, Lang; Mann, R.; Maciejewski, E.; Narasimha, S.; O’Neil, P.; Rauch, S.E.; Ryan, Deborah A.; Toomey, J.; Tsou, L. Y.; Varekamp, P.; Wachnik, R.; Wagner, T.; Wu, Shien‐Yang; Yu, C. H.; Agnello, P.; Connolly, John B.; Crowder, S.; Davis, Charles R.; Ferguson, R. S.; Sekiguchi, A.; Su, L.T.; Goldblatt, R.; Chen, T.C.

doi:10.1109/vlsit.2000.852818

Cited by 21 publications

(6 citation statements)

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“…The inverters used in this work were fabricated with 0.13-m 1.2-V partially depleted silicon-on-insulator (SOI) technology, with m, m, and nm, for both PFET and NFET [3]. Constant voltage stresses (positive or negative) between 2.6-3.9 V were applied to the inverter input to provoke the oxide BD, with inverter output at ground and other terminals floating.…”

Section: Methodsmentioning

confidence: 99%

A model for gate-oxide breakdown in CMOS inverters

Rodrı́guez

Stathis

Linder

2003

IEEE Electron Device Lett.

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The effect of oxide breakdown (BD) on the performance of CMOS inverters has been investigated. The results show that the inverter performance can be affected by the BD in a different way depending on the stress polarity applied to the inverter input. In all the cases, the oxide BD conduction has been modeled as gate-to-diffusion leakage with a power-law formula of the type = , which was previously found to describe the BD in capacitor structures. This implies that the BD physics at oxide level is the same as that at circuit level.Index Terms-CMOS, dielectric breakdown, hard breakdown (HBD), leakage currents, oxide breakdown, oxide reliability.

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Section: Methodsmentioning

confidence: 99%

A model for gate-oxide breakdown in CMOS inverters

Rodrı́guez

Stathis

Linder

2003

IEEE Electron Device Lett.

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“…As we move forward, SOI CMOS technology development is completed for the 0.13-m generation [6,20] and has been initiated for the 0.1-m generation [7,27]. These technologies are simply the highest-performance CMOS in production.…”

Section: Futurementioning

confidence: 99%

“…A limited number (a few tens of thousands) of 32-bit PowerPC 750* microprocessors, using 0.22-m CMOS SOI, were also shipped to customers. Since then, the development has focused on 0.18-m [5], 0.13-m [6], and 0.1-m [7] CMOS SOI technologies, with a greatly increased customer base.…”

Section: Introductionmentioning

confidence: 99%

SOI technology for the GHz era

Shahidi

2002

IBM J. Res. & Dev.

173

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Silicon-on-insulator (SOI) CMOS offers a 20-35% performance gain over bulk CMOS. High-performance microprocessors using SOI CMOS have been commercially available since 1998. As the technology moves to the 0.13-m generation, SOI is being used by more companies, and its application is spreading to lower-end microprocessors and SRAMs. In this paper, after giving a short history of SOI in IBM, we describe the reasons for performance improvement with SOI, and its scalability to the 0.1-m generation and beyond. Some of the recent applications of SOI in high-end microprocessors and its upcoming uses in low-power, radio-frequency (rf) CMOS, embedded DRAM (EDRAM), and the integration of vertical SiGe bipolar devices on SOI are described. As we move to the 0.1-m generation and beyond, SOI is expected to be the technology of choice for system-on-a-chip applications which require high-performance CMOS, low-power, embedded memory, and bipolar devices.

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“…In order to compare different technologies, two different CMOS 6T SRAM cells were investigated, using a 0.18-m/1.5-V bulk technology [4] and a 0.13-m/1.2-V partially depleted SOI technology [5]. Cell transfer ratios (width ratio of n-FET/pass-gate) are approximately 2-2.4.…”

Section: Detailsmentioning

confidence: 99%

The impact of gate-oxide breakdown on SRAM stability

Rodrı́guez

Stathis

Linder

et al. 2002

IEEE Electron Device Lett.

117

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We have investigated the effects of oxide soft breakdown (SBD) on the stability of CMOS 6T SRAM cells. Gate-to-diffusion leakage currents of 20-50 A at the n-FET source can result in a 50% reduction of noise margin. Breakdown at other locations in the cell may be less deleterious depending on n-FET width. This approach gives targets for tolerable values of leakage caused by gate-oxide breakdown. Index Terms-Dielectric breakdown, hard breakdown, leakage currents, MOS devices, oxide reliability, soft breakdown, SRAM.

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A high performance 0.13 μm SOI CMOS technology with Cu interconnects and low-k BEOL dielectric

Cited by 21 publications

References 0 publications

A model for gate-oxide breakdown in CMOS inverters

A model for gate-oxide breakdown in CMOS inverters

SOI technology for the GHz era

The impact of gate-oxide breakdown on SRAM stability

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