A high-level model of embedded flash energy consumption

Abstract

The alignment of code in the flash memory of deeply embedded SoCs can have a large impact on the total energy consumption of a computation. We investigate the effect of code alignment in six SoCs and find that a large proportion of this energy (up to 15% of total SoC energy consumption) can be saved by changes to the alignment. A flexible model is created to predict the read-access energy consumption of flash memory on deeply embedded SoCs, where code is executed in place. This model uses the instruction level memory accesses performed by the processor to calculate the flash energy consumption of a sequence of instructions. We derive the model parameters for five SoCs and validate them. The error is as low as 5%, with a 11% average normalized RMS deviation overall. The scope for using this model to optimize code alignment is explored across a range of benchmarks and SoCs. Analysis shows that over 30% of loops can be better aligned. This can significantly reduce energy while increasing code size by less than 4%. We conclude that this effect has potential as an effective optimization, saving significant energy in deeply embedded SoCs

Optimizing the flash-RAM energy trade-off in deeply embedded systems

“…Thus actual measurements are taken to verify the efficacy of the final code. Effects such as position dependent energy consumption in memory [13] and large variability between supposedly identical processors [26] necessitate evaluation with real, instrumented hardware.…”

Configurable Reprogramming Methodology for Embedded Low-Power Devices

“…Some works criticized this solution for an inefficient use of the program memory [4]. More jumps between pages in the memory cause more energy to be consumed, as activation of a different page consumes more power than activation of a different block within the same page [13].…”

Effective Over-the-Air Reprogramming for Low-Power Devices in Cyber-Physical Systems

“…Compiler alterations led to more instructions, thus worse execution times and some linker alterations resulted in fragmented program memory. Calls to functions in different parts of flash memory can lead to worse energy consumption as activation of different flash regions requires additional energy [10]. When considering many different devices and platforms in CPS, compiler and linker alterations would be required for every different platform.…”

“…There are many parameters that must be taken into account. The energy model proposed and validated in [10] is focused on embedded flash memories. The flash memory controller activates different regions of flash.…”