A high-level DRAM timing, power and area exploration tool

Naji, Omar; Weis, Christian; Jung, Matthias; Wehn, Norbert; Hansson, Andreas

doi:10.1109/samos.2015.7363670

Cited by 20 publications

(7 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For eight layers, this adds up to 32Gb, thus allowing 32 H-Cubes. The timing, current, and area values of the presented custom 3D DRAM for the 28 nm process with the TSV pitch of 40 μm are extracted from DRAMSpec [20,21], and the exact area dimension of each H-Cube is shown in Fig. 8.…”

Section: Dimensioning the Bcumentioning

confidence: 99%

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex

Stathis

Sudarshan

Yang

et al. 2020

J Sign Process Syst

Self Cite

View full text Add to dashboard Cite

The Artificial Neural Networks (ANNs), like CNN/DNN and LSTM, are not biologically plausible. Despite their initial success, they cannot attain the cognitive capabilities enabled by the dynamic hierarchical associative memory systems of biological brains. The biologically plausible spiking brain models, e.g., cortex, basal ganglia, and amygdala, have a greater potential to achieve biological brain like cognitive capabilities. Bayesian Confidence Propagation Neural Network (BCPNN) is a biologically plausible spiking model of the cortex. A human-scale model of BCPNN in real-time requires 162 TFlop/s, 50 TBs of synaptic weight storage to be accessed with a bandwidth of 200 TBs. The spiking bandwidth is relatively modest at 250 GBs/s. A hand-optimized implementation of rodent scale BCPNN has been done on Tesla K80 GPUs require 3 kWs, we extrapolate from that a human scale network will require 3 MWs. These power numbers rule out such implementations for field deployment as cognition engines in embedded systems. The key innovation that this paper reports is that it is feasible and affordable to implement real-time BCPNN as a custom tiled application-specific integrated circuit (ASIC) in 28 nm technology with custom 3D DRAM - eBrainII - that consumes 3 kW for human scale and 12 watts for rodent scale. Such implementations eminently fulfill the demands for field deployment.

show abstract

Section: Dimensioning the Bcumentioning

confidence: 99%

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex

Stathis

Sudarshan

Yang

et al. 2020

J Sign Process Syst

Self Cite

View full text Add to dashboard Cite

show abstract

“…• DRAM Power Model: Since DRAMs contribute significantly to the power consumption of today's systems [9,27], there is a need for accurate power modeling. For our framework we use DRAMPower [4,5], which uses either parameters from datasheets, estimated via DRAMSpec [33] or measurements to model DRAM power. • Thermal Model: 3D packaging of systems like Wide I/O DRAM starts to break down the memory and bandwidth walls.…”

Section: Approximate Drammentioning

confidence: 99%

Design of Efficient, Dependable SoCs Based on a Cross-Layer-Reliability Approach with Emphasis on Wireless Communication as Application and DRAM Memories

Weis

Gimmler-Dumont²,

Jung

et al. 2020

Dependable Embedded Systems

Self Cite

View full text Add to dashboard Cite

Many applications show an inherent error resilience due to their probabilistic behavior. This inherent error resilience can be exploited to reduce the design margin for advanced technology nodes resulting in more energy and area efficient implementation. We present in this chapter a cross-layer approach for efficient reliability management in wireless baseband processing with special emphasis on memories since memories are most susceptible to dependability problems. A multiple-antenna (MIMO) system will be used as design example. Further on we focus on DRAMs (Dynamic Random Access Memories). All today’s computing systems rely on dependable DRAMs. In the future DRAM memories will become more undependable due to further scaling. This has to be counterbalanced with higher refresh rates, which leads to a higher DRAM power consumption. Recent research activities resulted in the concept of “approximate DRAM” to save power and improve performance by lowering the refresh rate or disabling refresh completely. Here, we present a holistic simulation environment for investigations on approximate DRAM and show the impact on error-resilient applications.

show abstract

“…The sorted fault addresses allow us to process BSVG in parallel, so the delay in both the serial and parallel approaches is constant. Note that the delay of BSVG could be hidden within the latency of the column address decoding, which is significantly longer than 1 ns because the BSVG can work independently regardless of the column access [10] in our decoupled design.…”

Section: Performance Evaluationmentioning

confidence: 99%

A decoupled bit shifting technique using data encoding/decoding for DRAM redundancy repair

Choi

Jun

Kim

et al. 2017

IEICE Electron. Express

View full text Add to dashboard Cite

Redundancy repairs are commonly used to support fault tolerance in DRAM systems and recently, the processor performance has been greatly improved, so DRAM access latency has become an important issue. However, existing redundancy repairs using shift logic have difficulty in further reducing the latency due to their design limitations. In this paper, we propose a novel, decoupled bit shifting technique that uses data encoding and decoding to resolve this limitation. Our technique decouples the conventional shifting logic into two units, a bit selection vector generator (BSVG) and a data manipulation unit (DMU), to reduce the latency overhead of the shifting logic. Our technique can apply the BSVG in parallel with other logic consuming long latency operations, thereby reducing the total latency compared to conventional shifting logic. We implement both serial and parallel approaches to demonstrate that the parallel approach performs significantly better than the serial one in terms of delay, area, and dynamic power consumption. The experimental results show that our bit shifting technique is applicable for redundancy repair technique in state-of-the-art DRAM architectures.

show abstract

A high-level DRAM timing, power and area exploration tool

Cited by 20 publications

References 6 publications

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex

Design of Efficient, Dependable SoCs Based on a Cross-Layer-Reliability Approach with Emphasis on Wireless Communication as Application and DRAM Memories

A decoupled bit shifting technique using data encoding/decoding for DRAM redundancy repair

Contact Info

Product

Resources

About