A High-Level Design Flow for Locally Body Biased Asynchronous Circuits

Abstract

Fully Depleted Silicon on Insulator (FDSOI) technologies offer new possibilities for power management, especially with dynamic body biasing. Traditional strategies are based on a large body bias generator, which drives the IP back-gates thanks to a dedicated and often complex power management system. As asynchronous circuits use local synchronizations with handshake components, which activate only the processing parts, it is possible to take advantage of these handshake signals to implement a simple and fine-grain body biasing strategy. Instead of driving IPs with a large body bias generator, we use tiny distributed generators, locally activating small body bias regions when the circuit is processing data. These latter are based on level-shifters and implemented as standard cells. Thus, we propose a high-level design flow associating asynchronous circuits and a local body biasing strategy, which does not require complex body bias management. Indeed, the local handshake signals directly control our dedicated body bias generators. Moreover, Place and Route operations are facilitated by the use of standard cell generators. The simulations show the flow efficiency, a finer grain body biasing and a significant power reduction.

Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP

“…The standard rule-based and top-down synthesis flow [1][2][3][4][5][6] is adopted regularly for realizing various arithmetic and logical functions, including higher operand bit-widths. However, these methods neither allow any room to augment custom cells toward arriving at the hierarchical design nor offer any design-space exploration to realize the hardwarereliable design.…”