A High Definition Motion JPEG Encoder Based on Epuma Platform

Zhang, Yanjun; Zhou, Wei; Liu, Zhenyu; Wang, Siye; Liu, Dake

doi:10.1016/j.proeng.2012.01.317

Cited by 3 publications

(5 citation statements)

References 4 publications

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“…All computing steps necessary for M-JPEG have been included, except for Huffman encoding/decoding, which in our implementation has been offloaded to a hardware accelerator. Results for a full implementation on a FPGA prototype of ePUMA can be found in [89], where an M-JPEG encoder compresses data with resolution 1920 × 1080 at 30 fps, using a configuration with 4 MPE cores.…”

Section: M-jpegmentioning

confidence: 99%

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Sohl

2015

Linköping Studies in Science and Technology. Dissertations

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Modern signal processing systems require more and more processing capacity as times goes on. Previously, large increases in speed and power efficiency have come from process technology improvements. However, lately the gain from process improvements have been greatly reduced.Currently, the way forward for high-performance systems is to use specialized hardware and/or parallel designs.Application Specific Integrated Circuits (ASICs) have long been used to accelerate the processing of tasks that are too computationally heavy for more general processors. The problem with ASICs is that they are costly to develop and verify, and the product life time can be limited with newer standards. Since they are very specific the applicable domain is very narrow.More general processors are more flexible and can easily adapt to perform the functions of ASIC based designs. However, the generality comes with a performance cost that renders general designs unusable for some tasks. The question then becomes, how general can a processor be while still being power efficient and fast enough for some particular domain?Application Specific Instruction set Processors (ASIPs) are processors that target a specific application domain, and can offer enough performance with power efficiency and silicon cost that is comparable to ASICs.The flexibility allows for the same hardware design to be used over several system designs, and also for multiple functions in the same system, if some functions are not used simultaneously.iii iv One problem with ASIPs is that they are more difficult to program than a general purpose processor, given that we want efficient software.Utilizing all of the features that give an ASIP its performance advantage can be difficult at times, and new tools and methods for programming them are needed.This thesis will present ePUMA (embedded Parallel DSP platform with Unique Memory Access), an ASIP architecture that targets algorithms with predictable data access. These kinds of algorithms are very common in e.g. baseband processing or multimedia applications. The primary focus will be on the specific features of ePUMA that are utilized to achieve high performance, and how it is possible to automatically utilize them using tools. The most significant features include data permutation for conflict-free data access, and utilization of address generation features for overhead free code execution. This sometimes requires specific information; for example the exact sequences of addresses in memory that are accessed, or that some operations may be performed in parallel. This is not always available when writing code using the traditional way with traditional languages, e.g. C, as extracting this information is still a very active research topic. In the near future at least, the way that software is written needs to change to exploit all hardware features, but in many cases in a positive way. Often the problem with current methods is that code is overly specific, and that a more general abstractions are actually easier to ge...

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Section: M-jpegmentioning

confidence: 99%

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Sohl

2015

Linköping Studies in Science and Technology. Dissertations

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“…The applications include a Motion JPEG encoder [20], an MPEG-2 decoder [21], and an LTE downlink baseband processing unit. Other DSP kernels like matrix multiplication [22] and convolutional decoder [23] are also mapped to the parallel DSP.…”

Section: Application Analysis and Implementationmentioning

confidence: 99%

“…In addition to the above implementations, we also collaborate with other research groups at Linköping University and Beijing Institute of Technology to develop applications and demonstrations on ePUMA in the area of computer graphics [85][86] [87], multimedia applications [20], and general DSP kernels [88][89].…”

Section: Other Applications On Epumamentioning

confidence: 99%

Low Overhead Memory Subsystem Design for a Multicore Parallel DSP Processor

Wang¹

2014

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Cover imageCombined Star and Ring onchip interconnection of the ePUMA multicore DSP.Parts of this thesis are reprinted with permission from the IEEE.Printed by UniTryck, Linköping University Linköping, Sweden, 2014 AbstractThe physical scaling following Moore's law is saturated while the requirement on computing keeps growing. The gain from improving silicon technology is only the shrinking of the silicon area, and the speed- We have so far proved by applications that most DSP algorithms, such as filters, vector/matrix operations, transforms, and arithmetic functions, can achieve computing efficiency over 70% on the ePUMA platform.And the non-address stream network provides equivalent communication bandwidth by less than 30% implementation cost of a crossbar interconnection. PrefaceThis thesis includes the following papers published during my research • Jian Wang, Joar Sohl, Olof Kraigher, and Dake Liu. ePUMA: A novel embedded parallel DSP platform for predictable computing.

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“…This is mainly because memory transfers can be performed in parallel with computing, and the master processor and cluster controllers can perform most of the control operations. One such successful experiment is the implementation of an MJPEG-based web camera [143].…”

Section: Parallel Programming Frameworkmentioning

confidence: 99%

“…The author has been directly or indirectly involved in other implementations, such as motion-JPEG encoding [143], MPEG decoding [173], H.264 encoding [98], Long Term Evolution (LTE) processing [7], Euclidian distance transform calculation [174] and ePUMA for low-end graphics acceleration [175,176,177].…”

Section: Other Algorithms and Applicationsmentioning

confidence: 99%

Design of Energy-Efficient High-Performance ASIP-DSP Platforms

Karlsson¹

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Cover imageChip layout of an ePUMA system with 8 compute clusters, each with a local controller, 8 compute cores and 1536kB of local compute data memory. The complete chip contains 73 processor cores and occupies 45mm 2 in 28nm FDSOI technology.(Parts of this thesis are reprinted with permission from the IEEE.)Printed by LiU-Tryck, Linköping University Linköping, Sweden, 2016 AbstractIn the last ten years, limited clock frequency scaling and increasing power density has shifted IC design focus towards parallelism, heterogeneity and energy efficiency. Improving energy efficiency is by no means simple and it calls for a reevaluation of old design choices in processor architecture, and perhaps more importantly, development of new programming methodologies that exploit the features of modern architectures.This thesis discusses the design of energy-efficient digital signal processors with application-specific instructions sets, so-called ASIP-DSPs, and their programming tools. Target applications for such processors include, but are not limited to, communications, multimedia, image processing, intelligent vision and radar. These applications are often implemented by a limited set of kernel algorithms, whose performance and efficiency are critical to the application's success. At the same time, the extreme non-recurring engineering cost of system-on-chip designs means that product life-time must be kept as long as possible. Neither general-purpose processors nor non-programmable ASICs can meet both the flexibility and efficiency requirements, and ASIPs may instead be the best trade-off between all the conflicting goals.Traditional superscalar-and VLIW processor design focus has been to improve the throughput of fine-grained instructions, which results in high flexibility, but also high energy consumption. SIMD architectures, on the other hand, are often restricted by inefficient data access. The result is architectures which spend more energy and/or time on supporting operations rather than actual computing. In addition to the hardware design, this thesis also discusses parallel programming flow for distributed memory architectures and ePUMA application implementation. A DSP kernel programming language and its compiler is presented. This effectively demonstrates how kernels written in a high-level language can be translated into HOF instructions for very high processing efficiency. Populärvetenskaplig sammanfattning PrefaceThis thesis includes material from the following first-author publications:• Andréas Karlsson, Joar Sohl and Dake Liu.Energy-efficient sorting with the distributed memory architecture ePUMA. In Proceedings of the International Symposium on Parallel and Dis-tributed Processing with Applications (ISPA), 2015.• Andréas Karlsson, Joar Sohl and Dake Liu. Cost-efficient Mapping of 3-and 5-point DFTs toGeneral Baseband Processors. In Proceedings of the International Conference on Digital SignalProcessing (DSP), 2015.• Andréas Karlsson, Joar Sohl and Dake Liu. Software-based QPP Interleaving forBaseband DS...

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A High Definition Motion JPEG Encoder Based on Epuma Platform

Cited by 3 publications

References 4 publications

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Low Overhead Memory Subsystem Design for a Multicore Parallel DSP Processor

Design of Energy-Efficient High-Performance ASIP-DSP Platforms

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