A High-Current Kink Effect Free Z-Gate Poly–Si Thin-Film Transistor

Chien, Feng-Tso; Yu, Cheng-Hao; Chen, Chii-Wen; Cheng, Ching-Hwa; Kang, Tsung-Kuei; Chiu, Hsien‐Chin

doi:10.1109/led.2016.2566959

Cited by 4 publications

(15 citation statements)

References 18 publications

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“…Before evaluating the device's performance, ISE-TCAD was employed to gauge the difference between the conventional device and CES-TFT in the current path, drain electric field, and IIR [13][14][15][16]. The device IIR can be derived by a Chynoweth model and expressed [14] as…”

Section: Structure Simulation Device Measurement and Discussionmentioning

confidence: 99%

“…Figure 6 shows the simulated drain side electric field distributions for both structures at V ds = 5 V and V gs = −5 V. The leakage characteristics for both structures can be predicted by a negative gate bias simulation. The lower negative gate bias electric field helps this structure lower the leakage current [13,15]. Figure 7a,b depict the measured transfer curves and device output characteristics for both structures.…”

Section: Structure Simulation Device Measurement and Discussionmentioning

confidence: 99%

“…This study puts forth new current and electric field split TFT (CES-TFT) with partial thicker channel RSD [15] and bottom field plate (BFP) designs which do not require an extra mask and CMP process. The BFP connected to the drain can allure the electron and change the electron current path away from the high electric field area in the gate/drain region, thereby alleviating the impact ionization phenomenon.…”

Section: Introductionmentioning

confidence: 99%

“…The BFP connected to the drain can allure the electron and change the electron current path away from the high electric field area in the gate/drain region, thereby alleviating the impact ionization phenomenon. In addition, the partial thicker channel RSD structure in use is also conducive to reducing the drain electric field that contributes to the lowering of leakage current and suppression of the kink effect [15]. Figure 1 shows the design information and half cross section of the proposed structure.…”

Section: Introductionmentioning

confidence: 99%

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A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

et al. 2019

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In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field.Keywords: polycrystalline silicon (poly-Si); thin-film transistor (TFT); current and electric field split (CES); kink effect; field plate (FP); raised source/drain (RSD)

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Section: Structure Simulation Device Measurement and Discussionmentioning

confidence: 99%

Section: Structure Simulation Device Measurement and Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

et al. 2019

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“…But these designs required two CMP process steps, and the precise wet etching on the nitride sacrificial layer is difficult to control. Our previously study proposed a Z-gate structure to overcome the electric field superposition problem [16], but it still encountered a misalignment problem between the top and bottom gates.…”

Section: Introductionmentioning

confidence: 99%

Double-Gate Two-Step Source/Drain Poly-Si Thin-Film Transistor

et al. 2019

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A current improved and electric field reduced double-gate (DG) polycrystalline silicon thin-film transistor with two-step source/drain (DGTSD-TFT) design is proposed and demonstrated in this study. The two-step source/drain (TSD) design, which consists of a raised source/drain (RSD) area together with a partial gate overlapped lightly doped drain (P-GOLDD) structure, can lower the device drain electric field (DEF) to reveal a better device performance. Comparisons have been made with respect to a traditional single top gate (STG) device. The operation current of the proposed DGTSD-TFT is almost twice as large as that of the STG structure. The OFF-state leakage current and kink effect, as well as the ON/OFF current ratio for this double-gate and two-step source/drain structure, are also improved simultaneously because of a reduced DEF. A hot carrier stress test reveals that that two-step source/drain structure can achieve more stable device characteristics than the traditional device.

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Employing Drain-Bias Dependent Electrical Characteristics of Poly-Si TFTs to Improve Gray Level Control in Low Power AMOLED Displays

Huang

Fan

et al. 2019

IEEE J. Electron Devices Soc.

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With development of high efficiency organic light emitting diodes (OLEDs), and high mobility polycrystalline silicon (poly-Si) thin-film transistors (TFTs), low power and high resolution active matrix OLED (AMOLED) displays are becoming popular for mobile applications. However, they suffer from poor control of lower gray levels, with the driving TFT being operated in the subthreshold regime. In this paper, with help of non-ideal drain-bias dependent electrical characteristics of poly-Si TFTs, operation of the driving TFT can be moved out from the subthreshold regime to allow better control of the gray levels. As a result, a dynamic voltage scaling (DVS) method is developed, and shown to be able to improve the luminous uniformity for better image quality, while effectively reducing the static power consumption.INDEX TERMS Thin-film transistor, polycrystalline silicon (poly-Si), active matrix organic light emitting diode (AMOLED), low power.XINGHUA XU received the B.S. degree in engineering and the B.S. degree in economics from Xi'an Jiao Tong University in 2016. He is currently pursuing the M.S. degree with Shanghai Jiao Tong University. His current research interest includes AMOLED display driving.

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A High-Current Kink Effect Free Z-Gate Poly–Si Thin-Film Transistor

Cited by 4 publications

References 18 publications

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

A Low Impact Ionization Rate Poly-Si TFT with a Current and Electric Field Split Design

Double-Gate Two-Step Source/Drain Poly-Si Thin-Film Transistor

Employing Drain-Bias Dependent Electrical Characteristics of Poly-Si TFTs to Improve Gray Level Control in Low Power AMOLED Displays

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