11th Annual Gallium Arsenide Integrated Circuit (GaAs IC) Symposium
DOI: 10.1109/gaas.1989.69327
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A high aspect ratio via hole dry etching technology for high power GaAs MESFET

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Cited by 6 publications
(1 citation statement)
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“…The Source Island Via-hole (SIV) structure introduced by Mitsubishi[17] is effective for reducing both source parasitic inductance and thermal resistance. A high aspect ratio via-hole dry etching technology was applied to the K-band SIV FET in order to increase packing density [18]. Figure 10 shows an SEM photograph of a cross sectional view of the dry etched via-hole after inner metallization.…”
mentioning
confidence: 99%
“…The Source Island Via-hole (SIV) structure introduced by Mitsubishi[17] is effective for reducing both source parasitic inductance and thermal resistance. A high aspect ratio via-hole dry etching technology was applied to the K-band SIV FET in order to increase packing density [18]. Figure 10 shows an SEM photograph of a cross sectional view of the dry etched via-hole after inner metallization.…”
mentioning
confidence: 99%