A hierarchical test methodology for systems on chip

Li, Jin-Fu; Huang, Hsin-Jung; Chen, Jeng-Bin; Su, Chih-Pin; Wu, Cheng‐Wen; Cheng, Chien‐Hong; Chen, Shao-I; Hwang, Chi-Yi; Lin, Hsin‐Piao

doi:10.1109/mm.2002.1044301

Cited by 15 publications

(2 citation statements)

References 9 publications

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“…The IEEE Standard Testability Method for Embedded CoreBased Integrated Circuits (IEEE Standard 1500 [4]) addresses the specific challenges that come with testing deeply embedded reusable cores supplied by diverse providers, who often use different hardware description levels and mixed technologies [2], [5], [6]. The IEEE Standard 1500 defines a scalable standard architecture to facilitate and support the testing of embedded cores and the associated interconnect circuitry in a SoC.…”

Section: Introductionmentioning

confidence: 99%

IEEE Standard 1500 Compliance Verification for Embedded Cores

Benso

Carlo

Prinetto

et al. 2008

IEEE Trans. VLSI Syst.

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Core-based design and reuse are the two key elements for an efficient system-on-chip (SoC) development. Unfortunately, they also introduce new challenges in SoC testing, such as core test reuse and the need of a common test infrastructure working with cores originating from different vendors. The IEEE 1500 Standard for Embedded Core Testing addresses these issues by proposing a flexible hardware test wrapper architecture for embedded cores, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Several intellectual property providers have already announced IEEE Standard 1500 compliance in both existing and future design blocks. In this paper, we address the problem of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE Standard 1500. This step is mandatory to fully trust the wrapper functionalities in applying the test sequences to the core. We present a systematic methodology to build a verification framework for IEEE Standard 1500 compliant cores, allowing core providers and/or integrators to verify the compliance of their products (sold or purchased) to the standard.Index Terms-Electronic design automation (EDA) tools, IEEE 1500 Standard, unified modeling language (UML), verification of embedded cores.

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Section: Introductionmentioning

confidence: 99%

IEEE Standard 1500 Compliance Verification for Embedded Cores

Benso

Carlo

Prinetto

et al. 2008

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…The IEEE Standard Testability Method for Embedded Core-Based Integrated Circuits (IEEE std. 1500 [3]) addresses the specific challenges that come with testing deeply embedded reusable cores supplied by different providers, who often use different hardware description levels and mixed technologies [2] [4] [5]. It defines a comprehensive set of guidelines for building the core test infrastructure.…”

Section: Introductionmentioning

confidence: 99%

Automating the IEEE std. 1500 compliance verification for embedded cores

Benso

Carlo

Prinetto

et al. 2007

2007 IEEE International High Level Design Validation and Test Workshop

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The IEEE 1500 Standard for Embedded Core Testing proposes a very effective solution for testing modern System-On-Chip (SoC). It proposes a flexible hardware test wrapper architecture, together with a Core Test Language (CTL) used to describe the implemented wrapper functionalities. Already several IP providers have announced compliance in both existing and future design blocks. In this paper we address the challenge of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE std. 1500. This is a mandatory step to fully trust the wrapper functionalities in applying the test sequences to the core. The proposed solution aims at implementing a verification framework allowing core providers and/or integrators to automatically verify the compliancy of their products (sold or purchased) to the standard.

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Soc Testing and Design for Testability

Huang

Essential Issues in SOC Design

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A hierarchical test methodology for systems on chip

Cited by 15 publications

References 9 publications

IEEE Standard 1500 Compliance Verification for Embedded Cores

IEEE Standard 1500 Compliance Verification for Embedded Cores

Automating the IEEE std. 1500 compliance verification for embedded cores

Soc Testing and Design for Testability

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