Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors 1989

DOI: 10.1109/iccd.1989.63423

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A hierarchical constraint graph generation and compaction system for symbolic layout

A.A.J. de Lange

¹

,

Jan-Hendrik Lange

²

,

³

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Cited by 3 publications

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Efficient generation of diagonal constraints for 2-D mask compaction

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²

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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No abstract

Efficient generation of diagonal constraints for 2-D mask compaction

¹

,

²

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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No abstract

A new hierarchical layout compactor using simplified graph models

Kim¹,

Lee²,

[1992] Proceedings 29th ACM/IEEE Design Automation Conference

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A new hi erarchy-preservi ng hi erarchi cal compactor which can be used with either 1D or 2D leafcef1 compaction techniques has been devel oped.The compactor is applicable for hierarchical layouts which consist of a number of arrays of identical cells. The hierarchy is maintained throughout the compaction process so that all the instances of a subarray of identical cells have the same shape after compaction.Currently a hierarchical compactor based on the suggested simplified graph model has been developed and experimental results on several benchmark examples show that the proposed method is satisfactory.

An application specific IC for digital signal processing: the floating point pipeline CORDIC processor

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et al.

[Proceedings] EURO ASIC `90

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No abstract

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