A Heterogeneous Parallel Framework for Domain-Specific Languages

Brown, Kevin; Sujeeth, Arvind K.; Lee, Hyouk Joong; Rompf, Tiark; Chafi, Hassan; Odersky, Martin; Olukotun, Kunle

doi:10.1109/pact.2011.15

Cited by 152 publications

(82 citation statements)

References 31 publications

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“…This process involves mapping of parallelism, performing optimizations such as fusion of operations and finally code generation. This approach is used by a many systems such as Copperhead [5], Delite [3], Accelerate [6,15], LiquidMetal [9], HiDP [21], Halide [16] and NOVA [8].…”

Section: Related Work and Motivationmentioning

confidence: 99%

LIFT: A functional data-parallel IR for high-performance GPU code generation

Steuwer

Remmelg

Dubach

2017

2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

102

113

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Parallel patterns (e.g., map, reduce) have gained traction as an abstraction for targeting parallel accelerators and are a promising answer to the performance portability problem. However, compiling high-level programs into efficient lowlevel parallel code is challenging. Current approaches start from a high-level parallel IR and proceed to emit GPU code directly in one big step. Fixed strategies are used to optimize and map parallelism exploiting properties of a particular GPU generation leading to performance portability issues.We introduce the Lift IR, a new data-parallel IR which encodes OpenCL-specific constructs as functional patterns. Our prior work has shown that this functional nature simplifies the exploration of optimizations and mapping of parallelism from portable high-level programs using rewrite-rules. This paper describes how Lift IR programs are compiled into efficient OpenCL code. This is non-trivial as many performance sensitive details such as memory allocation, array accesses or synchronization are not explicitly represented in the Lift IR. We present techniques which overcome this challenge by exploiting the pattern's high-level semantics. Our evaluation shows that the Lift IR is flexible enough to express GPU programs with complex optimizations achieving performance on par with manually optimized code.

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Section: Related Work and Motivationmentioning

confidence: 99%

LIFT: A functional data-parallel IR for high-performance GPU code generation

Steuwer

Remmelg

Dubach

2017

2017 IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

102

113

View full text Add to dashboard Cite

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“…The DSL application (Scala code) is input into a Delite framework compiler framework [43] which runs a scalac to convert the DSL into Java bytecode. The produced Java bytecode is then executed (staged) to create Intermediate Representation (IR) and perform optimizations.…”

Section: A Dsl and High-level Compilationmentioning

confidence: 99%

Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language

Tsoeunyane¹,

Winberg²,

Inggs³

2017

International Journal of Reconfigurable Computing

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This paper reports on the design and implementation of an open-source library of parameterizable and reusable Hardware Description Language (HDL) Intellectual Property (IP) cores designed for the development of Software-Defined Radio (SDR) applications that are deployed on FPGA-based reconfigurable computing platforms. The library comprises a set of cores that were chosen, together with their parameters and interfacing schemas, based on recommendations from industry and academic SDR experts. The operation of the SDR cores is first validated and then benchmarked against two other cores libraries of a similar type to show that our cores do not take much more logic elements than existing cores and that they support a comparable maximum clock speed. Finally, we propose our design for a Domain-Specific Language (DSL) and supporting tool-flow, which we are in the process of building using our SDR library and the Delite DSL framework. We intend to take this DSL and supporting framework further to provide a rapid prototyping system for SDR application development to programmers not experienced in HDL coding. We conclude with a summary of the main characteristics of our SDR library and reflect on how our DSL tool-flow could assist other developers working in SDR field.

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“…Several environments have been proposed to facilitate the task of writing programs for heterogeneous SoCs, either by offering a single address space [Lin et al 2012;Diamos 2008], APIs for managing multiple versions of the same task for different accelerators [Diamos 2008;Augonnet et al 2009], OpenMP-like annotations to identify target accelerators [Dolbeau et al 2007], or domain-specific languages from which efficient accelerator code can be generated [Brown et al 2011]. However, all these methods require the programmer to be deeply involved in the task of writing programs for heterogeneous SoCs.…”

Section: Introductionmentioning

confidence: 99%

Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach

Fang¹,

Du²,

Fang³

et al. 2014

ACM Trans. Archit. Code Optim.

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Because of tight power and energy constraints, industry is progressively shifting toward heterogeneous system-on-chip (SoC) architectures composed of a mix of general-purpose cores along with a number of accelerators. However, such SoC architectures can be very challenging to efficiently program for the vast majority of programmers, due to numerous programming approaches and languages. Libraries, on the other hand, provide a simple way to let programmers take advantage of complex architectures, which does not require programmers to acquire new accelerator-specific or domain-specific languages. Increasingly, librarybased, also called algorithm-centric, programming approaches propose to generalize the usage of libraries and to compose programs around these libraries, instead of using libraries as mere complements.In this article, we present a software framework for achieving performance portability by leveraging a generalized library-based approach. Inspired by the notion of a component, as employed in software engineering and HW/SW codesign, we advocate nonexpert programmers to write simple wrapper code around existing libraries to provide simple but necessary semantic information to the runtime. To achieve performance portability, the runtime employs machine learning (simulated annealing) to select the most appropriate accelerator and its parameters for a given algorithm. This selection factors in the possibly complex composition of algorithms used in the application, the communication among the various accelerators, and the tradeoff between different objectives (i.e., accuracy, performance, and energy).Using a set of benchmarks run on a real heterogeneous SoC composed of a multicore processor and a GPU, we show that the runtime overhead is fairly small at 5.1% for the GPU and 6.4% for the multi-core. We then apply our accelerator selection approach to a simulated SoC platform containing multiple inexact accelerators. We show that accelerator selection together with hardware parameter tuning achieves an average 46.2% energy reduction and a speedup of 2.1× while meeting the desired application error target.

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A Heterogeneous Parallel Framework for Domain-Specific Languages

Cited by 152 publications

References 31 publications

LIFT: A functional data-parallel IR for high-performance GPU code generation

LIFT: A functional data-parallel IR for high-performance GPU code generation

Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language

Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach

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