A heterogeneous multiprocessor architecture for flexible media processing

Rutten, Martijn J.; Eijndhoven, J.T.J. van; Jaspers, E.G.T.; Wolf, Pieter van der; Gangwal, Om Prakash; Timmer, A.H.; Pol, Evert-Jan D.

doi:10.1109/mdt.2002.1018132

Cited by 66 publications

(32 citation statements)

References 8 publications

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“…Hence, in order to provide efficient transfer with high throughput, most existing multiprocessor systems employ DMA-like engines to facilitate messagepassing. Several early designs, such as Cray T3D [9] and Philips Eclipse [10], implement message-passing within a single address space and support large block transfer through a DMA engine. In several recent works, message-passing built on distributed memory architecture is proposed.…”

Section: Related Workmentioning

confidence: 99%

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Xiao

Isshiki

et al. 2012

IPSJ Transactions on System LSI Design Methodology

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Inter-processor communication and synchronization are critical problems in embedded multiprocessors. In order to achieve high-speed communication and low-latency synchronization, most recent designs employ dedicated hardware engines to support these communication protocols individually, which is complex, inflexible, and error prone. Thus, this paper motivates the optimization of inter-processor communication and synchronization by using application-specific instruction-set processor (ASIP) techniques. The proposed communication mechanism is based on a set of custom instructions coupled with a low-latency on-chip network, which provides efficient support for both data transfer and process synchronization. By using state-of-the-art ASIP design methodology, we embed the communication functionalities into a base processor, making the proposed mechanism feature ultra low overhead. More importantly, industry-standard compatible programming interfaces supporting both message-passing and shared-memory paradigms are exposed to end-users to ease the software porting. Experimental results show that the bandwidth of the proposed message-passing protocol can achieve up to 703 Mbyte/s @ 200 MHz, and the latency of the proposed synchronization protocol can be reduced by more than 81% when compared with the conventional approach. Moreover, as a case study, we also show the effectiveness of the proposed communication mechanism in a real-life embedded application, WiMedia UWB MAC.

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Section: Related Workmentioning

confidence: 99%

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Xiao

Isshiki

et al. 2012

IPSJ Transactions on System LSI Design Methodology

View full text Add to dashboard Cite

show abstract

“…Theelen et al [3] proposed a scalable multi-microprocessor architecture consisting of a number of identical master processors and configurable co-processors. Rutten et al [4] designed a heterogeneous multi-processor architecture template for digital multimedia applications. The multi-processor SoC architectures with high performance are able to meet the needs of application-specific requirements.…”

Section: Introductionmentioning

confidence: 99%

Multi-tasking of fuzzy inference processor through real-time context switching

Cao

Song

Shi

et al. 2009

2009 IEEE/ASME International Conference on Advanced Intelligent Mechatronics

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“…However, it is now increasingly being realized that conventional models, languages and design methodologies developed in the embedded systems domain are often not well-suited for implementing and analyzing these applications since they do not adequately exploit the notion of a "stream". To address this shortcoming, recently there has been a number of developments in the form of new "stream-centric" programming languages [40], compiler support [10], processor architectures [13,34] and design methodologies [20,23,27,43]. …”

Section: Introductionmentioning

confidence: 99%

Cache-Aware Timing Analysis of Streaming Applications

Chakraborty

Mitra

Roychoudhury

et al. 2007

19th Euromicro Conference on Real-Time Systems (ECRTS'07)

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Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. Such applications process potentially infinite streams of audio/video data or network packets and are found in a wide range of devices, starting from mobile phones to set-top boxes. Given a streaming application and an architecture, the timing analysis problem is to determine the timing properties of the processed data stream, given the timing properties of the input stream. This problem arises while determining many common performance metrics related to streaming applications and the mapping of such applications onto hardware architectures. Such metrics include the maximum delay experienced by any data item of the stream and the maximum backlog or the buffer requirement to store the incoming stream. Most of the previous work related to estimating or optimizing these metrics take a high-level view of the architecture and neglect micro-architectural features such as caches. In this paper, we show that an accurate estimation of these metrics, however, heavily relies on an appropriate modeling of the processor micro-architecture. Towards this, we present a novel framework for cacheaware timing analysis of stream processing applications. Our framework accurately models the evolution of the instruction cache of the underlying processor as a stream is processed, and the fact that the execution time involved in processing any data item depends on all the previous data items occurring in the stream. The main contribution of our method lies in its ability to seamlessly integrate program analysis techniques for micro-architectural modeling with known analytical methods for analyzing streaming applications, which treat the arrival/service of event streams as mathematical functions. This combination is powerful as it allows to model the code/cache-behavior of the streaming application, as well as the manner in which it is triggered by event arrivals. We employ our analysis method to an MPEG-2 encoder application and our experiments indicate that detailed modeling of the cache behavior is efficient, scalable and leads to more accurate timing/buffer size estimates.

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A heterogeneous multiprocessor architecture for flexible media processing

Cited by 66 publications

References 8 publications

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Optimized Communication and Synchronization for Embedded Multiprocessors Using ASIP Methodology

Multi-tasking of fuzzy inference processor through real-time context switching

Cache-Aware Timing Analysis of Streaming Applications

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