A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance

Abstract

Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-k dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-k dielectric material.

Electrical/Mechanical Modeling, Reliability Assessment, and Fabrication of FlexConnects: A MEMS-Based Compliant Chip-to-Substrate Interconnect

“…In our previous work [24], we have shown that the compliant G-Helix interconnects provide excellent opportunities for I/O customization based on electrical and mechanical requirements. In that work, it has been shown that employing interconnects with varying geometries across a single die is beneficial for the case of G-Helix interconnects.…”

“…Other advantages of this technology are as follows: 1) The fabrication process can be integrated into wafer-level fine-pitch batch processing; 2) the compliant interconnects will exert minimal force on the die pads and, therefore, will not crack or delaminate the low-K dielectric material on the die; 3) the interconnects will not require an underfill to accommodate the CTE mismatch between the die and the organic substrate, and as no underfill is used, the interconnects assembled with solder will be easily reworkable; by reflowing the solder, the chip can be removed from the substrate; 4) the interconnects can be fabricated at the wafer level and can therefore be potentially cost effective; also, as the interconnect fabrication uses conventional wafer fabrication infrastructure, there are no additional equipment/infrastructure costs; 5) as the interconnects are fabricated using lithography and electroplating, the interconnect dimensions and shape can be varied across the chip to accommodate the electrical, mechanical, and thermal requirements [24]; and 6) lead-free solder can be employed for the interconnect assembly to substrates, and therefore, the technology is environmentally friendly.…”

Reliability of spring interconnects for high channel-count polyimide electrode arrays

“…The microflex technique is used to establish electrical contact between the polyimide array and rigid substrate. Mechanically flexible interconnects with a fixed vertical height are widely investigated for flip-chip assembly on rigid substrates [25][26][27][28][29][30]. These interconnects minimize the thermo-mechanical stresses due to the mismatch in coefficients of thermal expansion and compensate for the non-planer surface of the substrate as well as potentially allowing rematable connections.…”