A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling

Fattah, Mohammad; Moghaddam, Soodeh Aghli; Mohammadi, Siamak

doi:10.1109/dsd.2009.212

Cited by 1 publication

(1 citation statement)

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“…The described router is modeled in gate level, using back-annotated library, and a 4x4 mesh network is constructed by behavioral model local IP cores as network traffic generators and analyzers. As interconnect links between two neighboring nodes, delay parameters of our delayinsensitive current-mode link proposed in [17] are used.…”

Section: ) Simulation Environment and Resultsmentioning

confidence: 99%

A High Throughput Low Power FIFO Used for GALS NoC Buffers

Fattah

Manian

Rahimi

et al. 2010

2010 IEEE Computer Society Annual Symposium on VLSI

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In Networks-on-chip, increasing the depth of routers' buffers even by a few stages can have a significant effect on average latency and saturation threshold of the network. However, the price to pay could be high in terms of power and silicon area. In this paper, we propose a low power, high throughput asynchronous FIFO suitable for buffers of GALS NoC routers. We consistently compare the performance with regards to power, area and throughput of our FIFO with some different FIFO structures, by exploring their design trade-offs with various number of stages and for different data lengths. These structures are simulated in 90nm CMOS technology with accurate spice simulations, where results show a low power consumption and latency, with a higher throughput. Finally, a back-annotated HDL model of a 4x4 mesh network, wherein a fully asynchronous router is implemented, shows better average latency, saturation threshold and power tradeoffs, using the proposed FIFO.

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Section: ) Simulation Environment and Resultsmentioning

confidence: 99%