A hardware implementation of real-time epileptic seizure detector on FPGA

Chen, Tsan-Jieh; Jeng, Chi; Chang, Shun-Ting; Chiueh, Herming; Liang, Sheng-Fu; Hsu, Yu-Wei; Chien, Tzu-Chieh

doi:10.1109/biocas.2011.6107718

Cited by 12 publications

(5 citation statements)

References 13 publications

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“…In neural recording, the artifact-induced problem of stimulation sometimes emerges and affects the function of biomedical devices for brain stimulation and recording (Asfour et al, 2007;Chen et al, 2011;Lin et al, 2013;Caldwell et al, 2019). As shown in Figure 1B, in the closed-loop neural recording and stimulation circuit for epileptic seizure detection and suppression, the stimulator is triggered, and it generates stimulation pulses in certain regions of the brain to suppress the epileptic seizure when an epileptic seizure episode is detected from the intracranial electroencephalogram (iEEG).…”

Section: Neural Recordingmentioning

confidence: 99%

Advances in Neural Recording and Stimulation Integrated Circuits

Liu

Mao

et al. 2021

Front. Neurosci.

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In the past few decades, driven by the increasing demands in the biomedical field aiming to cure neurological diseases and improve the quality of daily lives of the patients, researchers began to take advantage of the semiconductor technology to develop miniaturized and power-efficient chips for implantable applications. The emergence of the integrated circuits for neural prosthesis improves the treatment process of epilepsy, hearing loss, retinal damage, and other neurological diseases, which brings benefits to many patients. However, considering the safety and accuracy in the neural prosthesis process, there are many research directions. In the process of chip design, designers need to carefully analyze various parameters, and investigate different design techniques. This article presents the advances in neural recording and stimulation integrated circuits, including (1) a brief introduction of the basics of neural prosthesis circuits and the repair process in the bionic neural link, (2) a systematic introduction of the basic architecture and the latest technology of neural recording and stimulation integrated circuits, (3) a summary of the key issues of neural recording and stimulation integrated circuits, and (4) a discussion about the considerations of neural recording and stimulation circuit architecture selection and a discussion of future trends. The overview would help the designers to understand the latest performances in many aspects and to meet the design requirements better.

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Section: Neural Recordingmentioning

confidence: 99%

Advances in Neural Recording and Stimulation Integrated Circuits

Liu

Mao

et al. 2021

Front. Neurosci.

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“…To the best of our knowledge, all existing hardware implementations tasked for epileptic seizure detection and prediction have been realized using Field Programmable Gate Array (FPGA), CMOS and Very-large-scale Integration (VLSI) technologies. Most existing hardware implementations detect epileptic seizures using traditional Machine Learning (ML) algorithms such as Linear Least Squares (LLS) [7], Support Vector Machines (SVMs) [8], and k-nearest neighbors (kNN) [9]. We refer the reader to [10] for a comprehensive survey of epileptic seizure detection and prediction systems.…”

Section: Related Workmentioning

confidence: 99%

Towards Memristive Deep Learning Systems for Real-Time Mobile Epileptic Seizure Prediction

Lammie

Wang

Azghadi

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The unpredictability of seizures continues to distress many people with drug-resistant epilepsy. On account of recent technological advances, considerable efforts have been made using different hardware technologies to realize smart devices for the real-time detection and prediction of seizures. In this paper, we investigate the feasibility of using Memristive Deep Learning Systems (MDLSs) to perform real-time epileptic seizure prediction on the edge. Using the MemTorch simulation framework and the Children's Hospital Boston (CHB)-Massachusetts Institute of Technology (MIT) dataset we determine the performance of various simulated MDLS configurations. An average sensitivity of 77.4% and a Area Under the Receiver Operating Characteristic Curve (AUROC) of 0.85 are reported for the optimal configuration that can process Electroencephalogram (EEG) spectrograms with 7,680 samples in 1.408ms while consuming 0.0133W and occupying an area of 0.1269mm 2 in a 65nm Complementary Metal-Oxide-Semiconductor (CMOS) process.

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“…Existing BCIs [16,17,23,27,28] are designed for singlesite implantation and lack the ability to store adequately long historical neural data. Most BCIs [29,30] have additional limitations in that they have historically eschewed a subset of programmability, data rates, and flexibility to meet safe power constraints. These BCIs are specialized to a specific task and/or limit personalization of the algorithm [29,30].…”

Section: Introductionmentioning

confidence: 99%

“…Most BCIs [29,30] have additional limitations in that they have historically eschewed a subset of programmability, data rates, and flexibility to meet safe power constraints. These BCIs are specialized to a specific task and/or limit personalization of the algorithm [29,30]. Some support more programmability by sacrificing high data rates [16,17,27,28].…”

Section: Introductionmentioning

confidence: 99%

A Multi-Site Accelerator-Rich Processing Fabric for Scalable Brain-Computer Interfacing

Sriram¹,

Pothukuchi²,

Michał³

et al. 2023

Preprint

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Hull 1 is an accelerator-rich distributed implantable brain-computer interface (BCI) that reads biological neurons at data rates that are 2-3 orders of magnitude higher than the prior art, while supporting many neuroscientific applications. Prior approaches have restricted brain interfacing to tens of megabits per second in order to meet two constraints necessary for effective operation and safe long-term implantation-power dissipation under tens of milliwatts and response latencies in the tens of milliseconds. Hull also adheres to these constraints, but is able to interface with the brain at much higher data rates, thereby enabling, for the first time, BCI-driven research on and clinical treatment of brain-wide behaviors and diseases that require reading and stimulating many brain locations. Central to Hull's power efficiency is its realization as a distributed system of BCI nodes with accelerator-rich compute. Hull balances modular system layering with aggressive cross-layer hardware-software co-design to integrate compute, networking, and storage. The result is a lesson in designing networked distributed systems with hardware accelerators from the ground up.

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A hardware implementation of real-time epileptic seizure detector on FPGA

Cited by 12 publications

References 13 publications

Advances in Neural Recording and Stimulation Integrated Circuits

Advances in Neural Recording and Stimulation Integrated Circuits

Towards Memristive Deep Learning Systems for Real-Time Mobile Epileptic Seizure Prediction

A Multi-Site Accelerator-Rich Processing Fabric for Scalable Brain-Computer Interfacing

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