A hardware implementation of a binary neural image processor

Abstract

This paper presents the work that has resulted in the SAT processor; a dedicated hardware implementation of a binary neural image processor. The SAT processor is aimed speci cally at supporting the ADAM algorithm and is currently being integrated into a new version of the C-NNAP parallel image processor. The SAT processor performs binary matrix multiplications, a task that is computationally complex for a CPU with a standard instruction set. It can perform the matrix multiplication and thresholding between 100 and 200 times faster than the DSP32C that uses an in-house produced dedicated coprocessor. This speed-up will allow the SAT to process images of up to 220 x 220 pixels at 25-Hz frame rates.