A hardware genetic algorithm for the traveling salesman problem on Splash 2

Graham, Paul; Nelson, Brent

doi:10.1007/3-540-60294-1_129

Cited by 45 publications

(24 citation statements)

References 6 publications

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“…6, hardware GA with adaptive selection of crossover operator was implemented. Hardware GA has been applied to various problems such as disconnected closed loop extraction problem [7], TSP [8], and Set Coverage Problem [9]. Most of these existing methods including Ref.…”

Section: Related Workmentioning

confidence: 99%

Proposal of flexible implementation of genetic algorithms on FPGAs

Tachibana

Murata

Shibata

et al. 2007

Systems & Computers in Japan

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SUMMARYGenetic Algorithms (GA) can be used for various applications including complex computations such as combinatory optimization problems. Such GA applications are desired to be available to information appliances with poor resources by implementing them on dedicated hardware chips like FPGA. In this paper, we propose a method to efficiently design and implement GA applications on FPGA. Our method consists mainly of a parallel and pipelined architecture suitable for various GA applications and a model to predict the size of the synthesized hardware circuits from various parameter values such as the size of the problem and the number of parallel pipelines. In order to facilitate hardware design, we have implemented two tools. The first tool uses our prediction model and calculates parameter values with which the hardware circuits can be synthesized on a specified FPGA device. The second tool generates the RT level VHDL description when the parameter values are given. In order to show efficiency of the proposed method, we have applied our method to the Knapsack Problem and Traveling Salesman Problem. As a result, we have confirmed that the circuits synthesized with our tools achieve high performance on gate level simulation and low power consumption, and that our prediction model predicts the sizes of the synthesized circuits accurately enough for practical use.

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Section: Related Workmentioning

confidence: 99%

Proposal of flexible implementation of genetic algorithms on FPGAs

Tachibana

Murata

Shibata

et al. 2007

Systems & Computers in Japan

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“…In the next clock 2, w 13 4 is again referred to for td 2 . Then, in clock 4, the granular cell value is updated to w 13 4 as trained by td 1 . In clock 5, the result of training for w 13 4 is used in update for td 2 , not w 13 4′ .…”

Section: Problems In Pbga/cmacmentioning

confidence: 99%

“…Many application examples have been reported [4][5][6][7][8][9][10][11][12]. The genetic algorithm (GA), a form of evolutionary computation, is a technique of optimal solution search which is suited to global search [10].…”

Section: Introductionmentioning

confidence: 99%

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Cerebellar model arithmetic computer with pseudo‐bacterial genetic algorithm and its hardware acceleration

Miwa¹,

Furuhashi

Matsuzaki

et al. 2004

Systems & Computers in Japan

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SUMMARYThe cerebellar model arithmetic computer (CMAC) is a kind of neural network that is capable of high-speed learning. In the use of the CMAC, various parameters must be defined, but it is difficult to set the parameters adequately. The pseudo-bacterial genetic algorithm (PBGA) is a kind of evolutionary computation which offers local search. This paper considers adequate determination of the location of the boundary line, which is one of the parameters of the CMAC. For that purpose the PBGA is applied, and PBGA/CMAC, which realizes the efficient search of the boundary line of the CMAC, is proposed. Furthermore, since PBGA/CMAC requires a large amount of computation, a hardware implementation is considered in order to improve the computation speed. The computation involved in the learning rules of the CMAC is divided into four stages, and the structure is implemented as a pipeline. The pipeline implementation produces read-after-write hazards for the granular cell values. However, it is shown that the difference in performance from conventional CMAC learning rule is small, indicating the possibility of achieving high-speed learning. The speed of PBGA/CMAC hardware is improved to 140 times the speed of operation by software. In order to present a guide for PBGA/CMAC hardware, the hardware volume is evaluated, and it is shown that it can be implemented with precision sufficient for practice.

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“…This algorithm can be applied to combination optimiza-tion problems, NP-hard problems, and so on. Up to now, some architecture of hardware for GA has been proposed [4][5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Genetic algorithm with dynamic variable number of individuals and accuracy

Tsukahara

Kanasugi

2009

Int. J. Control Autom. Syst.

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This paper proposes a novel processor for genetic algorithm (GA) that can dynamically change number of individuals and accuracy. In conventional GA, number of population and accuracy are fixed. However, the accuracy of solution is low at first-half stage. Therefore, the number of population is doubled at expense of the accuracy of solution, and the searching ability is improved at first-stage in the proposed GA processor. Then, the number of population is reduced by half, and the accuracy is improved at second-half stage. As a result, the searching ability is improved. The proposed GA processor was designed and verified. The effectiveness of proposed method was confirmed by applying to the knapsack problem.

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A hardware genetic algorithm for the traveling salesman problem on Splash 2

Cited by 45 publications

References 6 publications

Proposal of flexible implementation of genetic algorithms on FPGAs

Proposal of flexible implementation of genetic algorithms on FPGAs

Cerebellar model arithmetic computer with pseudo‐bacterial genetic algorithm and its hardware acceleration

Genetic algorithm with dynamic variable number of individuals and accuracy

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