A Hardware-Efficient Synchronization in L-DACS1 for Aeronautical Communications

Abstract

Abstract-L-band digital aeronautical communication system type-1 (L-DACS1) is an emerging standard that aims at enhancing air traffic management by transitioning the traditional analog aeronautical communication systems to the superior and highly efficient digital domain. L-DACS1 employs modern and efficient orthogonal frequency-division multiplexing (OFDM) modulation technique to achieve more efficient and higher data rate in comparison to the existing aeronautical communication systems. However, the performance of OFDM systems is very sensitive to synchronization errors such as symbol timing offset (STO) and carrier frequency offset (CFO). STO and CFO estimations are extremely important for maintaining orthogonality among the subcarriers for the retrieval of information. This paper proposes a novel efficient hardware synchronizer for L-DACS1 systems that offers robust performance at low power and low hardware resource usage. Monte Carlo simulations show that the proposed synchronization algorithm provides accurate STO estimation as well as fractional CFO estimation. Implementation of the proposed synchronizer on a widely used field-programmable gate array (FPGA) (Xilinx xc7z020clg484-1) results in a very low hardware usage which consumed 6.5%, 3.7%, and 6.4% of the total number of lookup tables, flip-flops, and digital signal processing blocks, respectively. The dynamic power of the proposed synchronizer is below 1 mW.

New Spectrum Efficient Reconfigurable Filtered-OFDM Based L-Band Digital Aeronautical Communication System

“…Recently, few works dealing with the design and implementation of OFDM-based LDACS transceiver have been proposed [5,13,30,31,38,39]. In [30], novel correlation based synchronization approach for large carrier frequency offsets has been introduced, and its implementation on field programmable gate arrays (FPGA) has shown to consume lower area and power without compromising on the BER performance [31]. In [38], the design of LDACS transceiver via partial reconfiguration approach of the FPGA has been proposed.…”

“…Most of the existing works [5,10,30,31,38,39] deal with the improving the performance of the OFDM based LDACS.…”

High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction

“…The proposed strategies rely on hardware-efficient moving summation, multiplier-less circuitry and folded architectures. Moving summation is a recursive mathematic function that has been previously presented to calculate auto-correlation in wireless system [26]. In this paper, we manipulate the calculation of image moments in the moving summation's formula such that it can be effectively computed in hardware.…”

New Reconfigurable L-Band Digital Aeronautical Communication System

“…Recently, few works dealing with the design and implementation of OFDM-based LDACS transceiver has been proposed in [22,23,[33][34][35]. A hardware architecture of a novel synchronization method for LDACS in [33].…”