2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP &Amp; International Symposium on System-on-Chip (SoC) 2015
DOI: 10.1109/norchip.2015.7364362
|View full text |Cite
|
Sign up to set email alerts
|

A hardware architecture for the Branch and Bound Flow-Shop Scheduling algorithm

Abstract: Branch-and-Bound (B&B) algorithms are one of the most employed techniques in optimization problems. Its complexity increases exponentially with problem size and features a challenging dynamic memory management caused by recursive processing. Most solutions focus on parallel branch evaluation in multi-core CPUs or GPUs. To the best of our knowledge, to the date, no works have employed FPGAs to implement the BB technique. In this paper, we propose a mixed hardware-software architecture to solve the Flow-Shop Sc… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2016
2016
2023
2023

Publication Types

Select...
2
1

Relationship

0
3

Authors

Journals

citations
Cited by 3 publications
(1 citation statement)
references
References 6 publications
(10 reference statements)
0
1
0
Order By: Relevance
“…The PFSP has been frequently used as a test-case for parallel B&B algorithms, as the huge amount of generated nodes and the highly irregular structure of the search tree raise multiple challenges in terms of design and implementation on increasingly complex parallel architectures, e. g. grid computing (Mezmaz et al, 2007;Drozdowski et al, 2011;Bendjoudi et al, 2012), multicore CPUs (Mezmaz et al, 2014a;Gmys et al, 2016a), GPUs and many-core devices (Chakroun et al, 2013;Gmys et al, 2016b;Melab et al, 2018), clusters of GPUs (Vu and Derbel, 2016) or FPGAs (Daouri et al, 2015).…”
Section: Parallelismmentioning
confidence: 99%
“…The PFSP has been frequently used as a test-case for parallel B&B algorithms, as the huge amount of generated nodes and the highly irregular structure of the search tree raise multiple challenges in terms of design and implementation on increasingly complex parallel architectures, e. g. grid computing (Mezmaz et al, 2007;Drozdowski et al, 2011;Bendjoudi et al, 2012), multicore CPUs (Mezmaz et al, 2014a;Gmys et al, 2016a), GPUs and many-core devices (Chakroun et al, 2013;Gmys et al, 2016b;Melab et al, 2018), clusters of GPUs (Vu and Derbel, 2016) or FPGAs (Daouri et al, 2015).…”
Section: Parallelismmentioning
confidence: 99%