A Hardened-by-Design Technique for RF Digital Phase-Locked Loops

Loveless, T. D.; Massengill, L.W.; Bhuva, B. L.; Holman, W.T.; Witulski, A.F.; Boulghassoul, Y.

doi:10.1109/tns.2006.886203

Cited by 94 publications

(35 citation statements)

References 18 publications

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“…The vulnerability of conventional digital phase locked loops (D-PLLs) to a radiation particle strike was observed through simulations and experiments [27], [28]. The SET response of the PLL is dominated by the SET response of the charge pump module [27], [28].…”

Section: Previous Workmentioning

confidence: 99%

“…The SET response of the PLL is dominated by the SET response of the charge pump module [27], [28]. In [27], the authors present a hardened PLL operating at 700 MHz.…”

Section: Previous Workmentioning

confidence: 99%

“…The SET response of the PLL is dominated by the SET response of the charge pump module [27], [28]. In [27], the authors present a hardened PLL operating at 700 MHz. The authors study strikes only on the charge pump output, and observe that a 200 fC strike causes their hardened PLL to require 98ns (68 cycles) to recover lock, with at least one clock pulse being displaced by more than 2Π radians.…”

Section: Previous Workmentioning

confidence: 99%

“…We strike our nodes with a Q value of 250 fC (higher than that of [27]). Also, we utilize a more radiation sensitive 65nm process in comparison to a 130nm process for [27].…”

Section: Previous Workmentioning

confidence: 99%

“…We strike our nodes with a Q value of 250 fC (higher than that of [27]). Also, we utilize a more radiation sensitive 65nm process in comparison to a 130nm process for [27]. In the worst of all the strikes that we simulated, we find that we require 16 cycles of the VCO clock to return to the locked state.…”

Section: Previous Workmentioning

confidence: 99%

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A radiation tolerant Phase Locked Loop design for digital electronics

Kumar

Karkala

Garg

et al. 2009

2009 IEEE International Conference on Computer Design

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Abstract-With decreasing feature sizes, lowered supply voltages and increasing operating frequencies, the radiation tolerance of digital circuits is becoming an increasingly important problem. Many radiation hardening techniques have been presented in the literature for combinational as well as sequential logic. However, the radiation tolerance of clock generation circuitry has received scant attention to date. Recently, it has been shown that in the deep submicron regime, the clock network contributes significantly to the chip level Soft Error Rate (SER). The on-chip Phase Locked Loop (PLL) is particularly vulnerable to radiation strikes. In this paper, we present a radiation hardened PLL design. Each of the components of this design -the voltage controlled oscillator (VCO), the phase frequency detector (PFD) and the loop filter are designed in a radiation tolerant manner. Whenever possible, the circuit elements used in our PLL exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in a logic 0 to 1 (1 to 0) flip. By separating the PMOS and NMOS devices, and splitting the gate output into two signals, extreme high levels of radiation tolerance are obtained. Our PLL is tested for radiation immunity for critical charge values up to 250fC. Our results demonstrate that over a large number of radiation strikes on a number of sensitive nodes in our design, the worst case jitter is just 18%. In the worst case, our PLL returns to the locked state in 16 cycles of the VCO clock, after a radiation strike.

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Section: Previous Workmentioning

confidence: 99%

“…The SET response of the PLL is dominated by the SET response of the charge pump module [27], [28]. In [27], the authors present a hardened PLL operating at 700 MHz.…”

Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

“…We strike our nodes with a Q value of 250 fC (higher than that of [27]). Also, we utilize a more radiation sensitive 65nm process in comparison to a 130nm process for [27].…”

Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

See 3 more Smart Citations