A hard real-time capable multi-core SMT processor

Abstract

Hard real-time applications in safety critical domains require high performance and time analyzability. Multi-core processors are an answer to these demands, however task interferences make multi-cores more difficult to analyze from a worst-case execution time point of view than single-core processors. We propose a multi-core SMT processor that ensures a bounded maximum delay a task can suffer due to inter-task interferences. Multiple hard real-time tasks can be executed on different cores together with additional non real-time tasks. Our evaluation shows that the proposed MERASA multi-core provides predictability for hard real-time tasks and also high performance for non hard real-time tasks.

Multi-core Devices for Safety-critical Systems

“…At nanoscale level, timing fluctuations are due to physical properties such as temperature and require different techniques. The development of time predictable components provides a solid foundation to achieve device level temporal independence, simplify WCET analysis and software time composability [53]. However, with respect to time predictability and WCET, most of the research contributions can be classified as either "how things should be done" (e.g., time predictable components) or "how things can be done" (e.g., how to achieve temporal independence with generic devices).…”

“…• Hard real-time SMT core [53] implements Tricore instruction set [21] with two in-order super-scalar processor pipelines (integer and address) with multithreading support. This core is designed to ensure task level bounded maximum delay due to inter-task interference, between hard real-time and non-hard real-time tasks.…”

WCET-aware dynamic code management on scratchpads for Software-Managed Multicores

“…After excluding 1 for recursion and 22 for the number of functions, we use all of the remaining benchmarks, which are 8, from Mälardalen suite. MiBench suite is in general much larger in size and more complicated, susan 51440 9968 19 MiBench rijndael 23136 8028 7 MiBench statemate 11120 3568 8 Malardalen adpcm 10564 2896 17 Malardalen edn 5232 1972 9 Malardalen sha 4092 1276 8 MiBench compress 3936 1056 9 Malardalen lms 3696 900 8 Malardalen fft1 3304 1836 6 Malardalen dijkstra 2244 1052 6 MiBench matmult 1632 472 6 Malardalen cnt 1368 384 6 Malardalen and we were not able to generate the inlined CFGs of 6 benchmarks due to the presence of recursion or function pointers 3 , and 19 due to the complexity of compiled binaries 4 . We use the remaining 4 benchmarks in our evaluation.…”

“…Performance improvements in recent processor designs have mainly been driven by the multicore paradigm because of power and temperature limitations with single-core designs [3]. Some recent realtime systems architectures are moving towards multicore [4] or multithreaded [5], [6] designs. However, coherent caches, which are popular in traditional multicore platforms, are not a good fit for real-time systems.…”

Design of time-predictable architecture and DDR memory bank allocation for COTS multi-cores

“…The custom architecture described in Paolieri et al [26] proposes an interconnect design which follows a fixed pattern for cores to access the DDR memory. The design has a two-level arbitration scheme: inter-core (arbitrates between different cores) and intra-core (arbitrates within a core).…”