A Half-Rate Built-In Self-Test for High-Speed Serial Interface using a PRBS Generator and Checker

Bodha, Ram Ratnaker Reddy; Sarafi, Sahar; Kale, Ajinkya; Koberle, Michael; Sturm, Johannes

doi:10.1109/austrochip.2019.00019

Cited by 6 publications

(4 citation statements)

References 7 publications

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“…BERT electronic test equipment is employed to ensure that the high-speed serial interface transceivers function properly. To enable bit error rate monitoring without the need for off-chip subsystems such as memory and the PRBS generator, a half-rate BIST system is presented in [46].…”

Section: Testing and Debugging Of High-speed Interfacesmentioning

confidence: 99%

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A Knowledge Base Technique for Detecting Multiple High-Speed Serial Interface Synchronization Errors in Multiprocessor-Based Real-Time Embedded Systems

et al. 2022

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The heterogeneity of the multiple processing elements (PEs) is a feature of real-time embedded systems. General-purpose processors and several embedded processors, as well as dedicated high-speed interfaces, are among these elements. Communication between the processors is among the most significant characteristics of developing such complex systems. Furthermore, synchronization is a common issue during interprocessor communication in embedded systems. Debugging and testing such systems is time-consuming, difficult, and laborious, with the majority of the complexities centered on debugging real-time interprocessor communication, such as synchronization in terms of timing and accuracy. While the hardware design features of heterogeneous multiprocessor real-time embedded systems have received a lot of attention, the design and development of software-based solutions still have the potential to be addressed. In particular, software-based testing becomes challenging due to interprocessor communication and the synchronization of real-time applications. A knowledge-based technique that aids in testing high-speed serial interfaces in multiprocessor-based real-time embedded systems is proposed that needs debugging in real time while an application is running. It is becoming much more important to test and validate these interfaces in real time as the demand for high data transmission rates increases. The presented work uses a technique to simulate, create and enhance the knowledge base used as correlation-based error detection that reduces the development time. The proposed technique helps in detecting synchronization-related errors that occur during communication among multiple high-speed serial interfaces. The presented work also lists a series of experiments to validate the effectiveness of the proposed technique. The results show that the presented techniques are effective for error identification in real-time embedded systems.

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Section: Testing and Debugging Of High-speed Interfacesmentioning

confidence: 99%

“…Test only PCI-E Interface. Bodha et al (2019) [46] Half-rate built-in self-test (BIST) system for high-speed serial interface is used to enable bit error rate measurement.…”

Section: Testing and Debugging Of High-speed Interfacesmentioning

confidence: 99%

A Knowledge Base Technique for Detecting Multiple High-Speed Serial Interface Synchronization Errors in Multiprocessor-Based Real-Time Embedded Systems

et al. 2022

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“…The applied data streams are 2 7 À 1 random bit patterns, which are produced by an on-chip PRBS generator. 37 Figure 5 illustrates the differential voltage eye diagrams of the received data for both FDTs.…”

Section: Circuit Designmentioning

confidence: 99%

A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

Jarihani

Sturm

Tonello

2021

Circuit Theory & Apps

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This paper presents a high‐speed simultaneous bidirectional transceiver (SBT) for on‐chip wireline communications. A MOS hybrid transistor is utilized to split the received data from the superimposed signal at both ends of the on‐chip interconnection with the assistance of two drivers, namely main and auxiliary. Moreover, a high‐pass filter (HPF) is used as a differentiator to generate the echo cancelation signal. Consequently, the echo‐cancelation for simultaneous bidirectional signaling (SBS) is realized by the combination of the hybrid device and the differentiator. The proposed SBT has been designed and evaluated using 28‐nm CMOS technology over a narrow 5‐mm on‐chip interconnection, which possesses 11.9‐dB loss at the Nyquist frequency (half a bit rate). The energy‐efficiency of the proposed full‐duplex transceiver (FDT) for 20‐Gbps simultaneous bidirectional data transmission is 0.147 PJ/b/mm. The performance results show that the proposed SBT has better overall performance compared to the previous architectures reported in the literature to date. The layout of the presented SBT occupies a low area of 1574 μm2.

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“…The link has a width of 0.6 µm and a spacing of 1 µm with the adjacent shield layers. For this purpose, 2 7 − 1 random bit patterns have been generated using an on-chip PRBS generator [36] and sent to the drivers. The full-duplex operation of the transceiver is realized by transmitting the data streams from the FDT's at both ends of the interconnect.…”

Section: Post-layout Simulation Performancementioning

confidence: 99%

A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology

et al. 2020

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A high-speed full-duplex transceiver (FDT) over lossy on-chip interconnects is presented. The FDT employs a hybrid circuit to separate the inbound and outbound signals from each other and also performs echo-cancellation with the help of the main and the auxiliary drivers. A hybrid MOS device is utilized for impedance matching and conversion of the received voltage signal into a current signal for amplification. Moreover, a compensation capacitance ( C c ) is used at the output of the main driver to minimize the residual echo signal and achieve a higher data rate. The entire FDT architecture has been designed in TSMC 28 nm CMOS standard process with 0.9 V supply voltage. The performance results validate a 16 Gbps FD operation with a root-mean-square (RMS) jitter of 16.4 ps, and a power efficiency of 0.16 pJ/b/mm over a 5 mm on-chip interconnect without significant effect due to process-voltage-temperature (PVT) variations. To the best knowledge of the authors, this work shows the highest achievable full-duplex data rate, among the solutions reported in the literature to date, yet with low complexity, low layout area of 1581 μ m 2 and competitive power efficiency.

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A Half-Rate Built-In Self-Test for High-Speed Serial Interface using a PRBS Generator and Checker

Cited by 6 publications

References 7 publications

A Knowledge Base Technique for Detecting Multiple High-Speed Serial Interface Synchronization Errors in Multiprocessor-Based Real-Time Embedded Systems

A Knowledge Base Technique for Detecting Multiple High-Speed Serial Interface Synchronization Errors in Multiprocessor-Based Real-Time Embedded Systems

A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

A 16 Gbps, Full-Duplex Transceiver over Lossy On-Chip Interconnects in 28 nm CMOS Technology

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