A Half Adder Design Based on Ternary Multiplexers in Carbon Nano-Tube Field Effect Transistor (CNFET) Technology

Nikbakht, Elham; Dideban, Daryoosh; Moezi, Negin

doi:10.1149/2162-8777/abb588

Cited by 11 publications

(8 citation statements)

References 29 publications

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“…We have found 125 related papers [11–135], 20% of which have been published in IEEE journals. To be more specific, there are 15 IEEE Transactions [11–25], five IEEE Access [26–30], and two JSSC papers [31, 32].…”

Section: Literature Review and Backgroundmentioning

confidence: 99%

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Nemati

Kashani

Mirzaee

2023

IET Circuits, Devices & Syst

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The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or V DD . This way, in a single-V DD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count. K E Y W O R D Sadders, carbon nanotube field effect transistors, digital arithmetic, multivalued logic, multivalued logic circuits, ternary logicThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes.

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Section: Literature Review and Backgroundmentioning

confidence: 99%

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Nemati

Kashani

Mirzaee

2023

IET Circuits, Devices & Syst

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“…The three significant states of the ternary logic, along with their equivalent in the unbalanced mode are as below: "0" (0 V), "1" (V DD /2), and "2" (V DD ). 2 Unary operators are logic gates with oneinput/output. There exist twenty-seven (3 3 ) unary operators in the ternary logic.…”

Section: Introductionmentioning

confidence: 99%

“…The semiconductor industry has made enormous advancements as a result. [1][2][3] However, shrinking the feature size of the metal-oxidesemiconductor field-effect transistor (MOSFET) beyond 32 nm has led to critical problems such as high current leakage, large parametric variations, unreliability, short-channel effects, and decreasing gate control. [4][5][6][7] These problems reduce the suitability of the MOSFET for power/energy-efficient applications.…”

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confidence: 99%

“…23 The most efficient and appropriate method for MVL circuit design is to employ the multiple-threshold (multi-V th ). 2,5 In GNRFET devices, different V th can be revealed by setting the GNR width through the number of dimer lines, 24,25 making them an excellent candidate for MVL circuit implementation. However, with the latest tendency of extensive advantages in GNRFETs, within a short time, it may be required to utilize GNRs as the transistor channel.…”

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confidence: 99%

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A Power Efficient 32 nm Ternary Multiplier using Graphene Nanoribbon Field-Effect Transistor Technology

Rohani,

Emrani Zarandi

2023

ECS J. Solid State Sci. Technol.

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To address interconnections and energy issues associated with binary logic, designers are increasingly turning to ternary logic. One effective approach to implementing ternary logic-based circuits is to use a multiple-threshold voltage (multi-Vth) design. In particular, graphene nanoribbon (GNR)-based field-effect transistors (GNRFETs) are a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology for sub-32nm feature sizes, as GNRs have excellent properties that can overcome scaling issues in CMOS. This paper introduces a ternary multiplier implemented with 32 nm GNRFET technology, which demonstrates high efficiency with only 26 transistors. Simulation results show that the proposed multiplier improves power dissipation and product-delay-power (PDP) by at least 37.30% and 22.22%, respectively, compared to existing multiplier designs when run at 0.9V. Moreover, our proposed design is implemented with a carbon nanotube-based FET (CNTFET) technology. The GNRFET-based multiplier improved power and PDP by 41.77% and 30%, respectively in the cost of increasing the delay by 25%, compared to its CNTFET-based equivalent. Finally, we analyze the proposed multiplier under the process and environmental parameters variations of GNRFET technology. Overall, our results demonstrate the advantages of using GNRFET technology for implementing ternary logic-based circuits and provide insight into the impact of different design choices on performance.

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“…It is possible to address the first two criteria listed above by using different nanodevices such as the carbon nanotube FET (CNFET) [2], resonant tunnel diode (RTD) [3], rapid single quantum flux (RSQF) devices [4], single-electron transistor (SET) [5][6][7][8], etc. The current work considers different potential nanoelectronic binary multiplier design based on the single-electron threshold logic gate (SE-TLG) [9][10][11][12], the hybrid SET-CMOS approach [13][14][15], and CNFET-based designs [16,17]. The results are also compared with the conventional CMOS-based implementation of the same.…”

Section: Introductionmentioning

confidence: 99%

The design and performance of different nanoelectronic binary multipliers

Ghosh¹,

Jain

Sarkar

2021

J Comput Electron

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The design and performance of digital binary multipliers built using different types of nanoelectronic devices are investigated herein. Designs for 2 × 2 binary multipliers implemented using different technologies such as single-electron-threshold logic (SE-TLG), hybrid single-electron transistor/complementary metal-oxide-semiconductor (SET-CMOS), and carbon nanotube field-effect transistor (CNFET) devices are elaborated and presented with corresponding simulation results. The performance metrics considered for their comparison are the power consumption, the circuit area, the propagation delay, the operating temperature, the design platform, etc. The existing CMOS-based design is also compared with all three proposed designs. The comparative analysis indicates that the SE-TLG-based 2 × 2 binary multiplier design exhibits very low power consumption, the smallest area requirement, and the shortest propagation delay among the three. Meanwhile, the design based on hybrid SET-CMOS devices can operate at room temperature and delivers the optimal response in terms of all the other performance metrics when compared with the other circuit implementations considered herein. Further stability analysis of the designs based on SE-TLG and hybrid SET-CMOS devices is carried out to validate their performance.

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A Half Adder Design Based on Ternary Multiplexers in Carbon Nano-Tube Field Effect Transistor (CNFET) Technology

Cited by 11 publications

References 29 publications

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

A Power Efficient 32 nm Ternary Multiplier using Graphene Nanoribbon Field-Effect Transistor Technology

The design and performance of different nanoelectronic binary multipliers

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