A graph-theoretic approach to clock skew optimization

Abstract

This paper addresses the problem of minimizing the clock period of a circuit by optimizing the clock skews. We incorporate uncertainty factors and present a formulation that ensures that the optimization will be safe. In [l], the problem of clock period optimization is formulated as a linear program. We first propose an efficient graph-based solution that takes advantage of the structure of the problem. We also show that the results of [l] may result in exceedingly large skews, and propose a method to reduce these skews without sacrificing the optimality of the clock period. Experimental results on several ISCAS89 benchmark circuits are provided.

Clock period minimization of non-zero clock skew circuits

“…Then, we move to the procedure Delay_Insertion. We have p 3,4 =5 tu and p 1,3 = 0+(P MIN(2) /2)= 2.25 tu in G INS (2) . Thus, S INS(2) =(0,-2,-1,0,2) and P INS(2) =4 tu.…”

“…The clock period P is feasible, if and only if the corresponding constraint graph contains no positive cycle [2]. Based on this property, [2] proposed a binary search strategy to solve the optimal clock skew scheduling problem in polynomial time complexity.…”

“…Based on this property, [2] proposed a binary search strategy to solve the optimal clock skew scheduling problem in polynomial time complexity. The lower bound and upper bound of the clock period can be specified as 0 and longest path delay, respectively.…”

“…We have p 3,4 =0.5 tu in G MIN (2) and S MIN(2) =(0,0,0.5,1,2.5). Note that P MIN(2) =P INS(1) =4.5 tu.…”

“…Although the optimal clock skew scheduling [1,2] can enhance the circuit performance, it does not achieve the lower bound of the clock period. In fact, the maximum delay-to-register ratio of the cycles in the circuit gives a lower bound of the clock period.…”