A GPU implementation of a real-time MIMO detector

Abstract

Abstract-Multiple-input multiple-output (MIMO) is an existing technique that can significantly increase throughput of the system by employing multiple antennas at the transmitter and the receiver. Realizing maximum benefit from this technique requires computationally intensive detectors which poses significant challenges to receiver design. Furthermore, a flexible detector or multiple detectors are needed to handle different configurations. Graphical Processor Unit (GPU), a highly parallel commodity programmable co-processor, can deliver extremely high computation throughput and is well suited for signal processing applications. However, careful architecture aware design is needed to leverage performance offered by GPU. We show we can achieve good performance while maintaining flexibility by employing an optimized trellis-based MIMO detector on GPU.

High-Speed RS(255, 239) Decoder Based on LCC Decoding

“…Next, the throughput of the hard-output FSD implementation for a 4 × 4 was evaluated and compared to the one of the trellis-based detector proposed in [28], which considered the Nvidia 9600 GT GPU with 64 cores at 1.9 GHz. In addition, the proposed approach was also compared to the FSD GPU implementation reported in [18], by executing the CUDA code delivered by the authors in our GPU for the N c = 300 example case.…”

“…Note that this parameter was previously used to assess other implementations on GPU such as the ones in [23,28], thus, it allows a fair comparison among implementations. Moreover, the runtime evaluation exposes whether a given implementation guarantees the real-time requirements of a certain wireless standard.…”

“…Thus, the final step finds within this list the min- Table 1 Throughput and runtime of the FSD proposed implementation in the Nvidia Tesla C2070 GPU for a 4 × 4 system for different configurations compared to trellis-based detector results in [28] and the FSD results in [18]. imum distances of paths having the counter bits and computes the log 2 M · n T LLRs.…”

“…Signal processing for wireless communication systems is also a field which requires high computation capabilities. Additionally to the traditional use of digital sig- nal processors (DSP) and field programmable gate arrays (FPGA), GPUs are becoming very useful to develop software-defined-radio platforms [3,4,19], highthroughput schemes such as the trellis-based hard-and soft-output MIMO detectors proposed in [23,28,29] or the fast decoding schemes for LDPC codes presented in [13,21]. This is due to the cost-effectiveness of GPUs together with their huge capability of parallel processing.…”

MultiSphere: Massively Parallel Tree Search for Large Sphere Decoders

“…Wu et al [10] and Josza et al [11] attempt to also parallelize the low-dimensional MIMO detection process, on GPUs. However, Wu et al use a Trellis-decoder-like approximation of the SD which is not efficient for dense modulations and large MIMO systems, and Jósza et al perform aggressive and nearly exhaustive parallel search of multiple subtrees without accounting for the overall complexity and by exhaustively trying different partitioning configurations.…”