A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits

Fu, Rongliang; Wang, Mengmeng; Kan, Yirong; Yoshikawa, Nobuyuki; Ho, Tsung-Yi; Chen, Olivia

doi:10.1145/3566097.3567936

Cited by 7 publications

(8 citation statements)

References 8 publications

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“…Column "Baseline" is the most conservative constraints used in related works [2]- [6], [16], i.e., path balancing and fanout branching, plus an additional but realistic constraint that the network depth must be a multiple of p clk = 4 5 . Column "A" uses the improved D-latch design discussed in Section III-C, but still adopts path balancing.…”

Section: B Experimental Results On Constraint Relaxationmentioning

confidence: 99%

“…Existing works on AQFP sequential architectural design [14], [15], logic synthesis [2], [16]- [20], and buffer insertion-optimization [3]- [6] conventionally adopt a more conservative set of constraints: path balancing and fanout branching. Notice that fulfilling path balancing, with an additional constraint that d(N ′ ) mod p clk = 0, implies fulfilling phase alignment with Φ ro = {0}.…”

Section: B Phase Alignment Instead Of Path Balancingmentioning

confidence: 99%

“…Starting as a postprocessing step with relatively light-weight optimization [2], [16], the buffer insertion problem has been identified as a scheduling problem in [4]. As finding the optimal schedule in terms of buffer count is likely a NP-hard problem due to the interplay between buffers and splitters, various heuristics have been proposed and improvements were made rapidly [3]- [6]. All of these works assume the more conservative constraints, i.e., path balancing and fanout branching.…”

Section: Buffer/splitter Insertion and Optimizationmentioning

confidence: 99%

“…The AQFP splitter cell is based on the buffer cell and has the same cost of 2 JJs [2]. Thus, buffer insertion and splitter insertion are often considered together as an optimization problem [3]- [6]. In previous works, the buffer and splitter insertion problem has been formulated as follows: All paths should be balanced to the same length (path balancing), and all gates, including primary inputs, with multiple fanouts must be branched (fanout branching).…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Impact of Sequential Design on the Cost of Adiabatic Quantum-Flux Parametron Circuits

Lee,

Ayala,

De Micheli

2023

IEEE Trans. Appl. Supercond.

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Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family whose energy efficiency approaches theoretical limits. Because AQFP logic gates depend on a polyphase excitation current to perform their computation, gate fanins must arrive at the appropriate excitation phase. Such a technology constraint has conventionally been treated by inserting buffers to balance shorter paths. However, path balancing buffers account for a large portion of the circuit area, limiting the scalability of AQFP circuits. In this paper, we examine the necessity of AQFP design constraints and propose a more relaxed set of constraints which still guarantees the correct operation of AQFP sequential circuits. In particular, we propose to consider phase alignment instead of path balancing. Experimental results show that adopting the relaxed constraints reduces 73% of buffers on average, and up to 90% in some particularly-imbalanced benchmarks.

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Section: B Experimental Results On Constraint Relaxationmentioning

confidence: 99%

Section: B Phase Alignment Instead Of Path Balancingmentioning

confidence: 99%

Section: Buffer/splitter Insertion and Optimizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Impact of Sequential Design on the Cost of Adiabatic Quantum-Flux Parametron Circuits

Lee,

Ayala,

De Micheli

2023

IEEE Trans. Appl. Supercond.

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show abstract

“…For FBS in the path-balanced case, we first adapt the aforementioned general-case-ILP to account for the path-balancing constraints considering both scenarios where gate duplications are enabled and disabled. (The latter setting has been studied as the AQFP splitter/buffer insertion problem in a series of research work [15]- [18] as we describe in Section III. )…”

Section: Introductionmentioning

confidence: 99%

Fanout-Bounded Logic Synthesis for Emerging Technologies

Marakkalage,

De Micheli

2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In logic circuits, the number of fanouts a gate can drive is limited, and such limits are tighter in emerging technologies such as superconducting electronic circuits. Moreover, some such technologies, e.g., adiabatic quantum-flux-parametron (AQFP), pose additional constraints such as the need for balanced input-to-output paths to ensure proper signal propagation. In this work, targeting emerging technologies, we study the problem of re-synthesizing a logic network with bounded-fanout gates while minimizing area for a given depth. Namely, we 1) formulate the fanout-bounded synthesis (FBS) problem for a fixed target logic depth as an integer linear program (ILP), 2) propose a scalable top-down approach to construct a feasible solution to the ILP, and 3) extend both the exact and the heuristic approaches to the setting of path-balanced networks. Using our ILP, we obtain the global optimum solutions for a number of benchmarks that serve as ground truth for evaluating heuristic algorithms in both general and path-balanced FBS. Our heuristic algorithm for general FBS achieves an 11.82% better area than the state of the art with matching or better delays while attaining the optimum/near-optimum area for several considered benchmarks. For the path-balanced setting, our heuristic approach achieves 8.76% better delay on average with an average area improvement of 0.5% when using AQFP as the exemplar technology, while achieving more than 17% better delays on several benchmarks.

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DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits

Fu,

Chen,

et al. 2023

2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

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A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits

Cited by 7 publications

References 8 publications

Impact of Sequential Design on the Cost of Adiabatic Quantum-Flux Parametron Circuits

Impact of Sequential Design on the Cost of Adiabatic Quantum-Flux Parametron Circuits

Fanout-Bounded Logic Synthesis for Emerging Technologies

DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits

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