A Generalized Fault Tolerant Multilevel Inverter for Switch Open-Circuit Faults

Kumar, M Santosh; Borghate, Vijay B.; Sabyasachi, Sidharth

doi:10.1109/pedes.2018.8707742

Cited by 3 publications

(4 citation statements)

References 12 publications

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“…Markov chain theory (MCT) is a popular method to evaluate reliability. The reliability of TP42 is found to be higher than TP17 in [74], using MCT. It can be seen that the fault tolerance capability of TP42 is higher than TP17 in Tables 5 and 6.…”

Section: Total Standing Voltage (Tsv) and Cost Function (Cf)mentioning

confidence: 76%

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Single-Phase Fault Tolerant Multilevel Inverter Topologies—Comprehensive Review and Novel Comparative Factors

et al. 2022

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Multilevel inverters (MLIs) are used in a variety of industrial applications in high- and medium-voltage systems. The modularity, high-power output from medium voltages, and low harmonic content are some of the advantages of MLIs. The reliability of MLIs is quite important. The reliability is affected by different kinds of faults occurring in the MLIs. In MLI circuits, switching devices are the most vulnerable components and have a major involvement in all types of faults. As an outcome, it is necessary to take proper corrective action in the event of a fault. This work provides a comprehensive review of different fault tolerant (FT) solutions for MLIs in the event of switch fault. Moreover, various single-phase FT MLI topologies are reviewed, along with their constructional features, merits, and demerits. This work also proposes a comparison approach that integrates novel factors to account for fault tolerance quantitatively. A comparison investigation verifies the effectiveness of the proposed method. The FT operation of an existing five-level FT MLI topology is discussed, simulated, and experimentally verified.

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Section: Total Standing Voltage (Tsv) and Cost Function (Cf)mentioning

confidence: 76%

“…A single-phase five-level FT MLI is proposed in [74], and it is shown in Figure 39. It comprises two DC sources, one bidirectional switch, and six unidirectional switches.…”

Section: Tp42mentioning

confidence: 99%

Single-Phase Fault Tolerant Multilevel Inverter Topologies—Comprehensive Review and Novel Comparative Factors

et al. 2022

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“…These issues are addressed through the development of various reduced device count (RDC) topologies. In RDC MLI topologies, both cost and size were reduced, but switches were put under a greater amount of stress 11 . The low number of switches in RDC MLI topologies makes reliability a major concern.…”

Section: Introductionmentioning

confidence: 99%

“…stress. 11 The low number of switches in RDC MLI topologies makes reliability a major concern. RDC MLIs are highly susceptible to switch faults due to uneven voltage stresses on the switches.…”

mentioning

confidence: 99%

Performance evaluation of five‐level packed U‐cell inverter and its fault‐tolerant variants

Rehman,

Fahad,

Sarwar

et al. 2023

Circuit Theory & Apps

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SummaryIn the power electronics industry, reliability is of utmost importance to manufacturers. Power semiconductor devices are extensively utilized in multilevel inverters (MLIs), which results in increased failure probability. MLI structures have a significant impact on the system's overall reliability. MLIs with a high degree of reliability reduce system maintenance costs and improve efficiency and the life of the entire system. This paper presents a comprehensive evaluation of five‐level packed U‐cell (PUC5) inverter, modified five‐level PUC (MPUC5) inverter, and their fault‐tolerant (FT) variants with respect to reliability, degree of fault tolerance, power loss and efficiency, and cost. A more accurate reliability evaluation method is used in this work in which failure rates of each component of inverter topologies under healthy and post‐fault conditions are calculated. Hence, this method provides more accurate reliability function of an MLI topology as compared to other methods in which failure rates are assumed to be same for all switches. Typhoon HIL‐402 emulator is used to demonstrate the FT capabilities of topologies in hardware‐in‐the‐loop (HIL) environments.

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