A General Methodology for Synthesis and Verification of Register-Transfer Designs

Parker, Alice C.; Kurdahi, F.; Mlinar, Mitch

doi:10.1109/dac.1984.1585815

Cited by 11 publications

(6 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1: (1,2,4,11), (3,9), (5), (6,7,8), (10), (12), (13,14,15,16), (17) An illustration of the WCP algorithm applied to the weighted graph G of the same example code sequence to find the best design possible is given in the Appendix. The steps of the WCP algorithm for G are shown in Tables IV-XII.…”

Section: Weighted Cluster Partitioningmentioning

confidence: 99%

“…The steps of the WCP algorithm for G are shown in Tables IV-XII. However, using CP, seven additional partitionings into eight clusters are possible: 2: (1,2,4,11), (3), (5), (6,13,14,15), (7,8,9), (10), (12), (16,17) 3: (1,2,4,11), (3,9), (5), (6,7,8), (10,13,14,16), (12), (15), (17) 4: (1,2,4,11), (3), (5), (6,7,8), (9,10), (12), (13,14,16,17), (15) 5: (1,2,4,11), (3,6), (5), (7,8,9), (10), (12), (13,14,16,17), (15) 6: (1,2,4,11), (3,10), (5), (6), (7,8,9), (12), (13,14,16,17), (15)…”

Section: Weighted Cluster Partitioningmentioning

confidence: 99%

“…The pair (13,14) with the maximum number (7) of common neighbors, will be selected as the first candidate pair for this new cluster, with node 13 as the head of the cluster. After updating the list of edges (see Table VIII), it is found that the three pairs (6,13), (9,13) and (13,16) all have the same maximum number (4) of common neighbors. Furthermore, these three edges also all have the same number (9) of deleted edges.…”

Section: Appendixmentioning

confidence: 99%

“…After having chosen the candidate pair (6,7), the updated list of edges is shown in Table XII. Since the (new) head node 6 no longer appears in the list, we go back to step 2 of the WCP algorithm to form another cluster.…”

Section: Appendixmentioning

confidence: 99%

See 3 more Smart Citations

Cluster Partitioning Techniques for Data Path Synthesis

Chen

Sobelman

1994

VLSI Design

View full text Add to dashboard Cite

New, efficient algorithms for the automated synthesis of buses in data path design are presented. Modifications to the technique of Generalized Clique Partitioning (GCP) are discussed which lead to better designs and reduced computation time in large synthesis problems. The new approach, Weighted Cluster Partitioning (WCP), eliminates the need for backtracking. The algorithm guides the process of bus formation by assigning a higher weight to those interconnection units that should be combined first. The operation of the WCP algorithm is clearly demonstrated using a detailed example.A modified priority ordering in the selection of the candidate pair is also discussed which can improve the performance of GCP and WCP. We demonstrate that GCP II performs better than GCP, while WCP II consistently produces the best results of all these algorithms on a set of large synthesis examples.

show abstract

Section: Weighted Cluster Partitioningmentioning

confidence: 99%

Section: Weighted Cluster Partitioningmentioning

confidence: 99%

Section: Appendixmentioning

confidence: 99%

Section: Appendixmentioning

confidence: 99%

See 2 more Smart Citations

Cluster Partitioning Techniques for Data Path Synthesis

Chen

Sobelman

1994

VLSI Design

View full text Add to dashboard Cite

show abstract

“…Highlevel data path synthesis is concerned with the automatic generation and allocation of registers, ALUs and buses. Many approaches to automated data path synthesis have been proposed in the literature [1][2][3][4][5][6][7][8][9][10][11][17][18][19][20][21][22]]. However, current high-level synthesis tools lack the capability to handle early architectural design exploration so that the quality of designs produced by an automatic synthesis tool is not completely adequate for production use in comparison to manual design.…”

Section: Introductionmentioning

confidence: 99%

Using PDM on Multiport Memory Allocation in Data Path

Chen

1994

VLSI Design

View full text Add to dashboard Cite

A data path consists of memory elements (i.e. registers), data operators (i.e. ALUs) and interconnection units (i.e. buses) to control the data transfers in the digital system. Many approaches to memory synthesis have been proposed in the literature. However, only single port memory is considered for register allocation and no efficient synthesis approach for multiport memory synthesis. In this paper, an efficient method, Partitioned Dependence Matrix (PDM), is presented for memory synthesis which deals not only with single port memory synthesis but also multiport memory synthesis according to the design constraints. With suitable modifications, the proposed technique can also be applied to multiport memory synthesis in which the maximum number of read ports is different from the maximum number of write ports. Therefore, the entire design space is explored and has the capability to handle early architectural design exploration so that the quality of designs produced by an automatic synthesis tool is more adequate for production use in comparison to manual design. Illustrations of applying this method to different synthesis examples are presented. Results and improvements over previous techniques are demonstrated. A key element in our approach is the successful adoption of techniques originally developed for problems in test generation to the field of memory synthesis.

show abstract