A GaN-Integrated Galvanically Isolated Data Link Based on RF Planar Coupling With Voltage Combining for Gate-Driver Applications

Abstract

In this paper the design of a galvanically isolated data link for gate-driver applications in GaN technology is presented. The isolation channel exploits the near-field RF planar coupling between micro-antennas placed on two side-by-side co-packaged chips. Adopted package-scale isolation has several benefits i.e., the applicability to any integration technology and the capability to achieve both very high isolation rating and common-mode transient immunity by means of a proper distance between chips. The isolation channel adopts an RF carrier of 2 GHz that is modulated by a PWM signal. For the first time, a voltage-combining approach based on multiple antennas has been explored in a galvanically isolated data link. Specifically, the TX front-end consists of two capacitively coupled RF oscillators connected to two differential antennas designed for voltage combining. The RX front-end combines the transmitted RF signals by means of one differential antenna and extracts the PWM signal by means of a rectifier and an amplifier with a dynamic offset compensation. Emphasis is given to the design of micro-antennas, which is essential to minimize channel loss. The data link was tested by using a chip-on-board assembly to validate the proposed approach. The overall current consumption was lower than 4 mA for a PWM signal of 500 kHz and a duty cycle of 50%.INDEX TERMS Class D oscillator, current-reuse, dynamic offset compensation, galvanic isolation, GaN technology, gate driver, on-chip antennas, voltage-combining.