A GaAs integrated circuit for wideband digital quadrature demodulation

Abstract

AbstmctAn integrated circuit has been designed to perform signal processing functions including digital quadrature deniodulation on a sampled intermediate frequency signal in electronic warfare receivers. A -3 dB bandwidth exceeding 80 MHz is achieved using a fully pipelined, pardlel architecture implemented on a G A S gate array. lntmduc ti onQuadrature demodulation yields an efficient representation of ihe information contained in a bandpass IF signal and faci litates the extraction of amplitude and phase intitrmation. Analog quadrature demodulators are commonly used in radar, communications, and electronic warfare receivers although errors resulting from gain and phase imbalances between the inphase (I) and quadrature (Q) channels generally limit the attainable image rejection performance [ 11. Although digital signal processing techniques have potential performance advantages, they ha\ e been generally considered impractical for bandwidths greater than a few tens of MHz. This paper describes an Application Specific lntegrate'd Circuit (ASIC) intended to perform quadrature demodulation and other functions in eledronic warfare receivers. 11 explojts advances in digital signal processing algorithms and microelectronics technology to achieve a -3 dB bandwidth exceeding 80 Ml [z.ASIC Architecture Figure 1 is a simplified block diagram of the ASIC. Digitized IF data from an 8 bit analog-to-digital converter (ADC) is translated to GaAs logic levels and processed by a digital quadrature demodulator. The I and Q signals are deinultiplexed into even and odd data to halve the data rate, ard translated to TTL logic levels. The i and Q data are also processed by the signal detection block to determine thc presence of pulse signals h,aving a useful signal-to-noise 101 1 CH3577-4/95/0000-1011$01 .OO Q 1995 British Crown Copyright ratio. The buffer memory controller generates the address and control signals required to store the I and Q signal data immediately preceding, during, and following each pulse in a dual port static RAM. At the start of a pulse, a time stamp is generated by latching the output of a free running counter. The time stamp and addres? information required to access the I and Q signal data stored in the dual port RAM are stored in a separate external status FIFO memory. The signal data can be accessed for subsequent processing using straightfonvard memory mapped input/output techniques.Digital Quadlature Demodulation Algorithm Figure 2 shows the block diagram of a novel digital quadrature demodulation algorithm that has been evolved for implementation in special purpose hardware. It is conceptually similar to Rader's algorithm [2], but uses two highpass finite impulse response (FIR) filters having a relative phase shift of d 2 . The digitized IF signal data is sampled at a rate f, with the even and odd signal samples processed by separate filters. The pair of filters can be regarded a complex bandpass filter. Consequently, DC offsets from the ADC are suppressed and the performance requirements for the ana...