A Future of Integrated Electronics: Moving Off the Roadmap

Radack, D.J.; Zolper, J.C.

doi:10.1109/jproc.2007.911049

Cited by 9 publications

(5 citation statements)

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“…However, CMOS transistor scaling has started reaching its physical as well as economic limits (Radack and Zolper, 2008). Further scaling may prevent reliable binary operation of CMOS devices.…”

Section: Introductionmentioning

confidence: 99%

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Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

et al. 2014

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Recent advances in neuroscience together with nanoscale electronic device technology have resulted in huge interests in realizing brain-like computing hardwares using emerging nanoscale memory devices as synaptic elements. Although there has been experimental work that demonstrated the operation of nanoscale synaptic element at the single device level, network level studies have been limited to simulations. In this work, we demonstrate, using experiments, array level associative learning using phase change synaptic devices connected in a grid like configuration similar to the organization of the biological brain. Implementing Hebbian learning with phase change memory cells, the synaptic grid was able to store presented patterns and recall missing patterns in an associative brain-like fashion. We found that the system is robust to device variations, and large variations in cell resistance states can be accommodated by increasing the number of training epochs. We illustrated the tradeoff between variation tolerance of the network and the overall energy consumption, and found that energy consumption is decreased significantly for lower variation tolerance.

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Section: Introductionmentioning

confidence: 99%

“…Historical improvements in cost and performance of CMOS technology have relied on transistor scaling for decades. However, CMOS transistor scaling has started reaching its physical as well as economic limits (Radack and Zolper, 2008 ). Further scaling may prevent reliable binary operation of CMOS devices.…”

Section: Introductionmentioning

confidence: 99%

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

et al. 2014

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“…13 In recent years, the intersection of these trends, which could have had a significant impact, has begun to lose its validity to a large extent. 16 Due to the variability in power and voltage parameters required by devices, device scaling functions have become more challenging. 17 These challenges make it complex and difficult for devices to achieve optimal functionality.…”

Section: Introductionmentioning

confidence: 99%

“…The versatility of the Von Neumann architecture allows developers to create various complex computing systems by using CPUs and GPUs as modular components 13 . In recent years, the intersection of these trends, which could have had a significant impact, has begun to lose its validity to a large extent 16 . Due to the variability in power and voltage parameters required by devices, device scaling functions have become more challenging 17 .…”

Section: Introductionmentioning

confidence: 99%

An overview memristor based hardware accelerators for deep neural network

Gökgöz,

Gül,

Aydın

2024

Concurrency and Computation

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The prevalence of artificial intelligence applications using artificial neural network architectures for functions such as natural language processing, text prediction, object detection, speech, and image recognition has significantly increased in today's world. The computational functions performed by artificial neural networks in classical applications require intensive and large‐scale data movement between memory and processing units. Various software and hardware efforts are being made to perform these operations more efficiently. Despite these efforts, latency in data traffic and the substantial amount of energy consumed in data processing emerge as bottleneck disadvantages of the Von Neumann architecture. To overcome this bottleneck problem, it is necessary to develop hardware units specific to artificial intelligence applications. For this purpose, neuro‐inspired computing chips are believed to provide an effective approach by designing and integrating a set of features inspired by neurobiological systems at the hardware level to address the problems arising in artificial intelligence applications. The most notable among these approaches is memristor‐based neuromorphic computing systems. Memristors are seen as promising devices for hardware‐level improvement in terms of speed and energy because they possess non‐volatile memory and exhibit analog behavior. They enable effective storage and processing of synaptic weights, offering solutions for hardware‐level development. Taking into account these advantages of memristors, this study examines the research conducted on artificial neural networks and hardware that can directly perform deep learning functions and mimic the biological brain, which is different from classical systems in today's context.

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“…Modern system on chip (SoC) and network on chip (NoC) circuits are known by the integration of complex interconnect IP which brings more difficulties for the timing closure especially with the 16 nm technology node (and below) [1]. In parallel with the circuit performance, new technology nodes allowed a very high transistors' integration to have more functionalities inside smaller die area [2], which brings many manufacturing challenges before having production circuits. On the other hand, modern designs are power-constrained (e.g., IoT, Automotive, Mobile) [3,4].…”

Section: Introductionmentioning

confidence: 99%

A New Wire Optimization Approach for Power Reduction in Advanced Technology Nodes

Benallal¹,

Cherif²,

Chentouf³

et al. 2019

Adv. sci. technol. eng. syst. j.

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In advanced technologies nodes, starting from 28 nm to 7 nm and below, the power consumed of integrated circuits (ICs) becomes a big concern. Consequently, actual electronic design automation (EDA) tools are facing many challenges to have low power, reduced area and keep having required performance. To reach required success criteria, and because each picosecond and each picowatt counts, continuous development of new optimization technics is necessary. In this paper, we put to the experiment and analysis a new technic to reduce IC consumed power by optimizing its interconnections (nets). We propose an optimal algorithm and enhance it for a better compromise between having less consumed power and keep having a good design rout-ability. The new wire optimization technic based on an optimal choice of target nets for optimization: which is the list of nets consuming more than 80% of the total power in the interconnection without exceeding 30% of the total number of nets. Experiments on 14 test cases show an average total power saving of 5% on both dynamic and total power.

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A Future of Integrated Electronics: Moving Off the Roadmap

Cited by 9 publications

References 0 publications

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

An overview memristor based hardware accelerators for deep neural network

A New Wire Optimization Approach for Power Reduction in Advanced Technology Nodes

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