A fully integrated Class-E power amplifier in 0.13um CMOS technology

Khan, Hashim Raza; Qureshi, Abdul Raheem; Wahab, Q.

doi:10.1109/newcas.2011.5981257

Cited by 5 publications

(1 citation statement)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In addition, comparing to the designs proposed in [5] and [10], the inductance tuning is realized by single capacitor bank instead of two, subsequently, less number of controlling bits, easier control algorithm and significant reduction in chip area can be achieved. The silicon area is further reduced by proving DC feed supply to the transistors through balun inductors [11]. Although, due to differential topology two capacitor banks are required as the shunt capacitors but since they are driven from the same control signal, the number of control signals remains conserved.…”

Section: A Simplified Output Matching Networkmentioning

confidence: 99%

PWM with differential Class-E amplifier for efficiency enhancement at back-off power levels

Khan

Qureshi

Zafar

et al. 2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

Self Cite

View full text Add to dashboard Cite

A simplified output matching network for pulse width modulated Class-E Power Amplifier for efficiency enhancement at back-off power level is proposed. The shunt capacitance and the series inductance in the Class-E PA are realized through capacitor banks that are tuned according to the duty cycle to meet ZVS conditions. The differential PA design is implemented in 130 nm CMOS technology achieving maximum P out of 24.8 dBm at 1.8 GHz with PAE better than 38% at 50% duty cycle. The output power is modulated with the input duty cycle and provides 6.2 dB back-off power level keeping PAE almost constant around 38%.

show abstract

Section: A Simplified Output Matching Networkmentioning

confidence: 99%